[PATCH] D113967: [RISCV] Reverse the order of loading/storing callee-saved registers.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

In D113967#3137613 <https://reviews.llvm.org/D113967#3137613>, @asb wrote:

> In D113967#3135737 <https://reviews.llvm.org/D113967#3135737>, @jrtc27 wrote:
>
>> Though, I'm unconvinced about whether the hazard in the epilogue matters in practice. In a simple in-order micoarchitecture if restoring ra stalls then it doesn't matter where that is, you can't execute out-of-order. In a superscalar core you'll just speculate past the ret anyway, which should predict accurately for anything with a half-decent RAS, though I guess you'll have unresolved speculation for longer that might be an issue. Is there a particular microarchitecture you've measured an appreciable difference for this on?
>
> The target is probably cores using a microarchitecture similar to Rocket. It has a "non-blocking D-cache" where the integer pipeline won't stall upon a cache miss until the register value is actually read (provided there are sufficient MSHRs).

Can it actually issue additional loads in the meantime though, i.e. everything else that appears in between the restore and the stack adjustment? I wouldn't expect so for an in-order core, which is why I asked what I did. I'm struggling to see a case where this would ever matter.


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