[llvm] f2d402e - [NFC][AMDGPU][GlobalISel] Fix some legalizer tests
Mirko Brkusanin via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 17 05:27:39 PST 2021
Author: Mirko Brkusanin
Date: 2021-11-17T14:25:15+01:00
New Revision: f2d402e58b90eb2ee747ed96a2f7c5e7667023bd
URL: https://github.com/llvm/llvm-project/commit/f2d402e58b90eb2ee747ed96a2f7c5e7667023bd
DIFF: https://github.com/llvm/llvm-project/commit/f2d402e58b90eb2ee747ed96a2f7c5e7667023bd.diff
LOG: [NFC][AMDGPU][GlobalISel] Fix some legalizer tests
Instructions being tested were accidentally left dead.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
index f33f77cddd01..5fe62f8c302f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
@@ -54,19 +54,23 @@ body: |
; SI-LABEL: name: test_fceil_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI: $vgpr0 = COPY [[COPY]](s32)
+ ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
+ ; SI: $vgpr0 = COPY [[FCEIL]](s32)
; CI-LABEL: name: test_fceil_s32
; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CI: $vgpr0 = COPY [[COPY]](s32)
+ ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
+ ; CI: $vgpr0 = COPY [[FCEIL]](s32)
; VI-LABEL: name: test_fceil_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI: $vgpr0 = COPY [[COPY]](s32)
+ ; VI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
+ ; VI: $vgpr0 = COPY [[FCEIL]](s32)
; GFX9-LABEL: name: test_fceil_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9: $vgpr0 = COPY [[COPY]](s32)
+ ; GFX9: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
+ ; GFX9: $vgpr0 = COPY [[FCEIL]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FCEIL %0
- $vgpr0 = COPY %0
+ $vgpr0 = COPY %1
...
---
@@ -131,19 +135,73 @@ body: |
; SI-LABEL: name: test_fceil_v2s16
; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI: $vgpr0 = COPY [[COPY]](<2 x s16>)
+ ; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+ ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
+ ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
+ ; SI: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
+ ; SI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT1]]
+ ; SI: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL1]](s32)
+ ; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
+ ; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
+ ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
+ ; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; SI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-LABEL: name: test_fceil_v2s16
; CI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CI: $vgpr0 = COPY [[COPY]](<2 x s16>)
+ ; CI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; CI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+ ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
+ ; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
+ ; CI: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
+ ; CI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT1]]
+ ; CI: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL1]](s32)
+ ; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
+ ; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
+ ; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
+ ; CI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; CI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; VI-LABEL: name: test_fceil_v2s16
; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI: $vgpr0 = COPY [[COPY]](<2 x s16>)
+ ; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; VI: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
+ ; VI: [[FCEIL1:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC1]]
+ ; VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FCEIL]](s16)
+ ; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FCEIL1]](s16)
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
+ ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
+ ; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; VI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; GFX9-LABEL: name: test_fceil_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9: $vgpr0 = COPY [[COPY]](<2 x s16>)
+ ; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; GFX9: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
+ ; GFX9: [[FCEIL1:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC1]]
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
+ ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL1]](s16)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
+ ; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = G_FCEIL %0
- $vgpr0 = COPY %0
+ $vgpr0 = COPY %1
...
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
index 48f712f7076f..105d648c1206 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
@@ -39,13 +39,15 @@ body: |
; SI-LABEL: name: test_frint_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI: $vgpr0 = COPY [[COPY]](s32)
+ ; SI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[COPY]]
+ ; SI: $vgpr0 = COPY [[FRINT]](s32)
; CI-LABEL: name: test_frint_s32
; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CI: $vgpr0 = COPY [[COPY]](s32)
+ ; CI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[COPY]]
+ ; CI: $vgpr0 = COPY [[FRINT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FRINT %0
- $vgpr0 = COPY %0
+ $vgpr0 = COPY %1
...
---
@@ -85,13 +87,45 @@ body: |
; SI-LABEL: name: test_frint_v2s16
; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI: $vgpr0 = COPY [[COPY]](<2 x s16>)
+ ; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+ ; SI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT]]
+ ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT]](s32)
+ ; SI: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
+ ; SI: [[FRINT1:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT1]]
+ ; SI: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT1]](s32)
+ ; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
+ ; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
+ ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
+ ; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; SI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-LABEL: name: test_frint_v2s16
; CI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CI: $vgpr0 = COPY [[COPY]](<2 x s16>)
+ ; CI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; CI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+ ; CI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT]]
+ ; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT]](s32)
+ ; CI: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
+ ; CI: [[FRINT1:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT1]]
+ ; CI: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT1]](s32)
+ ; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
+ ; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
+ ; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
+ ; CI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; CI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = G_FRINT %0
- $vgpr0 = COPY %0
+ $vgpr0 = COPY %1
...
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
index 68b123a0e961..0fee4ec0316e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
@@ -54,19 +54,23 @@ body: |
; SI-LABEL: name: test_intrinsic_trunc_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI: $vgpr0 = COPY [[COPY]](s32)
+ ; SI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; SI: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32)
; CI-LABEL: name: test_intrinsic_trunc_s32
; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CI: $vgpr0 = COPY [[COPY]](s32)
+ ; CI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; CI: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32)
; VI-LABEL: name: test_intrinsic_trunc_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI: $vgpr0 = COPY [[COPY]](s32)
+ ; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; VI: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32)
; GFX9-LABEL: name: test_intrinsic_trunc_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9: $vgpr0 = COPY [[COPY]](s32)
+ ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX9: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC_TRUNC %0
- $vgpr0 = COPY %0
+ $vgpr0 = COPY %1
...
---
@@ -123,19 +127,73 @@ body: |
; SI-LABEL: name: test_intrinsic_trunc_v2s16
; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI: $vgpr0 = COPY [[COPY]](<2 x s16>)
+ ; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+ ; SI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
+ ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
+ ; SI: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
+ ; SI: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; SI: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
+ ; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
+ ; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
+ ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
+ ; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; SI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-LABEL: name: test_intrinsic_trunc_v2s16
; CI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CI: $vgpr0 = COPY [[COPY]](<2 x s16>)
+ ; CI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; CI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+ ; CI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
+ ; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
+ ; CI: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
+ ; CI: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; CI: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
+ ; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
+ ; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
+ ; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
+ ; CI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; CI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; VI-LABEL: name: test_intrinsic_trunc_v2s16
; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI: $vgpr0 = COPY [[COPY]](<2 x s16>)
+ ; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; VI: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
+ ; VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[INTRINSIC_TRUNC]](s16)
+ ; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[INTRINSIC_TRUNC1]](s16)
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
+ ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
+ ; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; VI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; GFX9-LABEL: name: test_intrinsic_trunc_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9: $vgpr0 = COPY [[COPY]](<2 x s16>)
+ ; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX9: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INTRINSIC_TRUNC]](s16)
+ ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[INTRINSIC_TRUNC1]](s16)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
+ ; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = G_INTRINSIC_TRUNC %0
- $vgpr0 = COPY %0
+ $vgpr0 = COPY %1
...
---
More information about the llvm-commits
mailing list