[PATCH] D114078: [X86] Add tests cases for or-lea with no common bits.
Omer Aviram via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 17 04:50:08 PST 2021
OmerAviram created this revision.
OmerAviram added reviewers: RKSimon, guyblank, alonkom.
Herald added a subscriber: pengfei.
OmerAviram requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
Added tests are permutations of the pattern: (X & ~M) or (Y & M).
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D114078
Files:
llvm/test/CodeGen/X86/or-lea.ll
Index: llvm/test/CodeGen/X86/or-lea.ll
===================================================================
--- llvm/test/CodeGen/X86/or-lea.ll
+++ llvm/test/CodeGen/X86/or-lea.ll
@@ -131,3 +131,84 @@
ret i64 %or
}
+; In the following pattern, lhs and rhs of the or instruction have no common bits.
+
+define i16 @or_and_and_1(i16 %x, i16 %y, i16 %z) {
+; CHECK-LABEL: or_and_and_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: andl %esi, %edx
+; CHECK-NEXT: notl %esi
+; CHECK-NEXT: andl %edi, %esi
+; CHECK-NEXT: orl %edx, %esi
+; CHECK-NEXT: leal 1(%rsi), %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %and1 = and i16 %z, %y
+ %xor = xor i16 %y, -1
+ %and2 = and i16 %x, %xor
+ %or = or i16 %and1, %and2
+ %inc = add i16 %or, 1
+ ret i16 %inc
+}
+
+define i16 @or_and_and_2(i16 %x, i16 %y, i16 %z) {
+; CHECK-LABEL: or_and_and_2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: andl %esi, %edx
+; CHECK-NEXT: notl %esi
+; CHECK-NEXT: andl %edi, %esi
+; CHECK-NEXT: orl %edx, %esi
+; CHECK-NEXT: leal 1(%rsi), %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %and1 = and i16 %z, %y
+ %xor = xor i16 %y, -1
+ %and2 = and i16 %xor, %x
+ %or = or i16 %and1, %and2
+ %inc = add i16 %or, 1
+ ret i16 %inc
+}
+
+define i16 @or_and_and_3(i16 %x, i16 %y, i16 %z) {
+; CHECK-LABEL: or_and_and_3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: andl %esi, %edi
+; CHECK-NEXT: notl %esi
+; CHECK-NEXT: andl %edx, %esi
+; CHECK-NEXT: orl %edi, %esi
+; CHECK-NEXT: leal 1(%rsi), %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %xor = xor i16 %y, -1
+ %and1 = and i16 %z, %xor
+ %and2 = and i16 %x, %y
+ %or = or i16 %and1, %and2
+ %inc = add i16 %or, 1
+ ret i16 %inc
+}
+
+define i16 @or_and_and_4(i16 %x, i16 %y, i16 %z) {
+; CHECK-LABEL: or_and_and_4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: andl %esi, %edi
+; CHECK-NEXT: notl %esi
+; CHECK-NEXT: andl %edx, %esi
+; CHECK-NEXT: orl %edi, %esi
+; CHECK-NEXT: leal 1(%rsi), %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %xor = xor i16 %y, -1
+ %and1 = and i16 %xor, %z
+ %and2 = and i16 %x, %y
+ %or = or i16 %and1, %and2
+ %inc = add i16 %or, 1
+ ret i16 %inc
+}
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