[llvm] 3264e95 - [CodeGen] Update LiveIntervals in TargetInstrInfo::convertToThreeAddress
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 17 02:29:27 PST 2021
Author: Jay Foad
Date: 2021-11-17T10:16:47Z
New Revision: 3264e95938ac01c2991697cdebf492d771914a97
URL: https://github.com/llvm/llvm-project/commit/3264e95938ac01c2991697cdebf492d771914a97
DIFF: https://github.com/llvm/llvm-project/commit/3264e95938ac01c2991697cdebf492d771914a97.diff
LOG: [CodeGen] Update LiveIntervals in TargetInstrInfo::convertToThreeAddress
Delegate updating of LiveIntervals to each target's
convertToThreeAddress implementation, instead of repairing LiveIntervals
after the fact in TwoAddressInstruction::convertInstTo3Addr.
Differential Revision: https://reviews.llvm.org/D113493
Added:
Modified:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.h
llvm/lib/Target/X86/X86FixupLEAs.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 1a70a4312a125..8bc730a3eda50 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -411,8 +411,12 @@ class TargetInstrInfo : public MCInstrInfo {
/// This method returns a null pointer if the transformation cannot be
/// performed, otherwise it returns the last new instruction.
///
+ /// If \p LIS is not nullptr, the LiveIntervals info should be updated for
+ /// replacing \p MI with new instructions, even though this function does not
+ /// remove MI.
virtual MachineInstr *convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const {
+ LiveVariables *LV,
+ LiveIntervals *LIS) const {
return nullptr;
}
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 6673de548de18..46cec5407565b 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -676,7 +676,7 @@ bool TwoAddressInstructionPass::convertInstTo3Addr(
MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
Register RegA, Register RegB, unsigned &Dist) {
MachineInstrSpan MIS(mi, MBB);
- MachineInstr *NewMI = TII->convertToThreeAddress(*mi, LV);
+ MachineInstr *NewMI = TII->convertToThreeAddress(*mi, LV, LIS);
if (!NewMI)
return false;
@@ -701,28 +701,8 @@ bool TwoAddressInstructionPass::convertInstTo3Addr(
std::make_pair(NewInstrNum, NewIdx));
}
- // If convertToThreeAddress created a single new instruction, assume it has
- // exactly the same effect on liveness as the old instruction. This is much
- // more efficient than calling repairIntervalsInRange.
- bool SingleInst = std::next(MIS.begin(), 2) == MIS.end();
- if (LIS && SingleInst)
- LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
-
- SmallVector<Register> OrigRegs;
- if (LIS && !SingleInst) {
- for (const MachineOperand &MO : mi->operands()) {
- if (MO.isReg())
- OrigRegs.push_back(MO.getReg());
- }
-
- LIS->RemoveMachineInstrFromMaps(*mi);
- }
-
MBB->erase(mi); // Nuke the old inst.
- if (LIS && !SingleInst)
- LIS->repairIntervalsInRange(MBB, MIS.begin(), MIS.end(), OrigRegs);
-
for (MachineInstr &MI : MIS)
DistanceMap.insert(std::make_pair(&MI, Dist++));
Dist--;
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index bb4f93d5a3c00..6b1c5d56379f5 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1392,7 +1392,7 @@ bool SIFoldOperands::tryFoldClamp(MachineInstr &MI) {
// Use of output modifiers forces VOP3 encoding for a VOP2 mac/fmac
// instruction, so we might as well convert it to the more flexible VOP3-only
// mad/fma form.
- if (TII->convertToThreeAddress(*Def, nullptr))
+ if (TII->convertToThreeAddress(*Def, nullptr, nullptr))
Def->eraseFromParent();
return true;
@@ -1537,7 +1537,7 @@ bool SIFoldOperands::tryFoldOMod(MachineInstr &MI) {
// Use of output modifiers forces VOP3 encoding for a VOP2 mac/fmac
// instruction, so we might as well convert it to the more flexible VOP3-only
// mad/fma form.
- if (TII->convertToThreeAddress(*Def, nullptr))
+ if (TII->convertToThreeAddress(*Def, nullptr, nullptr))
Def->eraseFromParent();
return true;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 778eefe92beec..37f269ccb6076 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -19,6 +19,7 @@
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineScheduler.h"
@@ -3122,7 +3123,8 @@ static void updateLiveVariables(LiveVariables *LV, MachineInstr &MI,
}
MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const {
+ LiveVariables *LV,
+ LiveIntervals *LIS) const {
unsigned Opc = MI.getOpcode();
bool IsF16 = false;
bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
@@ -3190,6 +3192,8 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
.add(*Src1)
.addImm(Imm);
updateLiveVariables(LV, MI, *MIB);
+ if (LIS)
+ LIS->ReplaceMachineInstrInMaps(MI, *MIB);
return MIB;
}
}
@@ -3204,6 +3208,8 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
.addImm(Imm)
.add(*Src2);
updateLiveVariables(LV, MI, *MIB);
+ if (LIS)
+ LIS->ReplaceMachineInstrInMaps(MI, *MIB);
return MIB;
}
}
@@ -3218,6 +3224,8 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
.addImm(Imm)
.add(*Src2);
updateLiveVariables(LV, MI, *MIB);
+ if (LIS)
+ LIS->ReplaceMachineInstrInMaps(MI, *MIB);
return MIB;
}
}
@@ -3241,6 +3249,8 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
.addImm(Clamp ? Clamp->getImm() : 0)
.addImm(Omod ? Omod->getImm() : 0);
updateLiveVariables(LV, MI, *MIB);
+ if (LIS)
+ LIS->ReplaceMachineInstrInMaps(MI, *MIB);
return MIB;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 1740a06275bea..dd9ea2b53ca2d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -340,8 +340,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
unsigned getMachineCSELookAheadLimit() const override { return 500; }
- MachineInstr *convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const override;
+ MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ LiveIntervals *LIS) const override;
bool isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB,
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 4a66b4fa060be..2d981be4cfc12 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -173,8 +173,9 @@ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
return MHR;
}
-MachineInstr *ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const {
+MachineInstr *
+ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ LiveIntervals *LIS) const {
// FIXME: Thumb2 support.
if (!EnableARM3Addr)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 04590f157b2bc..db9320962e811 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -120,8 +120,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
// if there is not such an opcode.
virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
- MachineInstr *convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const override;
+ MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ LiveIntervals *LIS) const override;
virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
const ARMSubtarget &getSubtarget() const { return Subtarget; }
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 92f81c14869bb..547d82550cacc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -19,6 +19,7 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/MemoryLocation.h"
+#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -1674,7 +1675,8 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)
MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const {
+ LiveVariables *LV,
+ LiveIntervals *LIS) const {
switch (MI.getOpcode()) {
default:
break;
@@ -1716,6 +1718,20 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
}
}
+ if (LIS) {
+ SlotIndex Idx = LIS->ReplaceMachineInstrInMaps(MI, *MIB);
+
+ if (MI.getOperand(0).isEarlyClobber()) {
+ // Use operand 1 was tied to early-clobber def operand 0, so its live
+ // interval could have ended at an early-clobber slot. Now they are not
+ // tied we need to update it to the normal register slot.
+ LiveInterval &LI = LIS->getInterval(MI.getOperand(1).getReg());
+ LiveRange::Segment *S = LI.getSegmentContaining(Idx);
+ if (S->end == Idx.getRegSlot(true))
+ S->end = Idx.getRegSlot();
+ }
+ }
+
return MIB;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index a2aeb32ccffd4..2bfad7844c430 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -160,8 +160,8 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
unsigned OpIdx1,
unsigned OpIdx2) const override;
- MachineInstr *convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const override;
+ MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ LiveIntervals *LIS) const override;
Register getVLENFactoredAmount(
MachineFunction &MF, MachineBasicBlock &MBB,
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 214b9291167ea..2bf80882fa612 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -943,8 +943,9 @@ static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI,
NewMI->setFlag(Flag);
}
-MachineInstr *SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const {
+MachineInstr *
+SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ LiveIntervals *LIS) const {
MachineBasicBlock *MBB = MI.getParent();
// Try to convert an AND into an RISBG-type instruction.
@@ -985,6 +986,8 @@ MachineInstr *SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI,
LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
}
}
+ if (LIS)
+ LIS->ReplaceMachineInstrInMaps(MI, *MIB);
transferDeadCC(&MI, MIB);
return MIB;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index 3b796dea52c45..396f56c7f59c0 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -272,8 +272,8 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
Register DestReg, int FrameIdx,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
- MachineInstr *convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const override;
+ MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ LiveIntervals *LIS) const override;
MachineInstr *
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
ArrayRef<unsigned> Ops,
diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp
index 3f60f5951ccba..9a63cffe0a092 100644
--- a/llvm/lib/Target/X86/X86FixupLEAs.cpp
+++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp
@@ -212,7 +212,7 @@ FixupLEAPass::postRAConvertToLEA(MachineBasicBlock &MBB,
// These instructions are all fine to convert.
break;
}
- return TII->convertToThreeAddress(MI, nullptr);
+ return TII->convertToThreeAddress(MI, nullptr, nullptr);
}
FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 769874d1b740e..2ac0a2d4433f0 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -19,6 +19,7 @@
#include "X86TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Sequence.h"
+#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineConstantPool.h"
@@ -1195,7 +1196,7 @@ inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
unsigned Opc, bool AllowSP, Register &NewSrc,
bool &isKill, MachineOperand &ImplicitOp,
- LiveVariables *LV) const {
+ LiveVariables *LV, LiveIntervals *LIS) const {
MachineFunction &MF = *MI.getParent()->getParent();
const TargetRegisterClass *RC;
if (AllowSP) {
@@ -1241,6 +1242,15 @@ bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
if (LV)
LV->replaceKillInstruction(SrcReg, MI, *Copy);
+
+ if (LIS) {
+ SlotIndex CopyIdx = LIS->InsertMachineInstrInMaps(*Copy);
+ SlotIndex Idx = LIS->getInstructionIndex(MI);
+ LiveInterval &LI = LIS->getInterval(SrcReg);
+ LiveRange::Segment *S = LI.getSegmentContaining(Idx);
+ if (S->end.getBaseIndex() == Idx)
+ S->end = CopyIdx.getRegSlot();
+ }
}
// We've set all the parameters without issue.
@@ -1250,6 +1260,7 @@ bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
MachineInstr &MI,
LiveVariables *LV,
+ LiveIntervals *LIS,
bool Is8BitOp) const {
// We handle 8-bit adds and various 16-bit opcodes in the switch below.
MachineBasicBlock &MBB = *MI.getParent();
@@ -1271,6 +1282,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
unsigned Opcode = X86::LEA64_32r;
Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
+ Register InRegLEA2;
// Build and insert into an implicit UNDEF value. This is OK because
// we will be shifting and then extracting the lower 8/16-bits.
@@ -1282,15 +1294,19 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
MachineBasicBlock::iterator MBBI = MI.getIterator();
Register Dest = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
+ Register Src2;
bool IsDead = MI.getOperand(0).isDead();
bool IsKill = MI.getOperand(1).isKill();
unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
- BuildMI(MBB, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
+ MachineInstr *ImpDef =
+ BuildMI(MBB, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
MachineInstr *InsMI =
BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
.addReg(InRegLEA, RegState::Define, SubReg)
.addReg(Src, getKillRegState(IsKill));
+ MachineInstr *ImpDef2 = nullptr;
+ MachineInstr *InsMI2 = nullptr;
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
@@ -1323,11 +1339,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
case X86::ADD8rr_DB:
case X86::ADD16rr:
case X86::ADD16rr_DB: {
- Register Src2 = MI.getOperand(2).getReg();
+ Src2 = MI.getOperand(2).getReg();
bool IsKill2 = MI.getOperand(2).isKill();
assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
- unsigned InRegLEA2 = 0;
- MachineInstr *InsMI2 = nullptr;
if (Src == Src2) {
// ADD8rr/ADD16rr killed %reg1028, %reg1028
// just a single insert_subreg.
@@ -1339,7 +1353,8 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
// Build and insert into an implicit UNDEF value. This is OK because
// we will be shifting and then extracting the lower 8/16-bits.
- BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
+ ImpDef2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF),
+ InRegLEA2);
InsMI2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
.addReg(InRegLEA2, RegState::Define, SubReg)
.addReg(Src2, getKillRegState(IsKill2));
@@ -1367,6 +1382,45 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
LV->replaceKillInstruction(Dest, MI, *ExtMI);
}
+ if (LIS) {
+ LIS->InsertMachineInstrInMaps(*ImpDef);
+ SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(*InsMI);
+ if (ImpDef2)
+ LIS->InsertMachineInstrInMaps(*ImpDef2);
+ SlotIndex Ins2Idx;
+ if (InsMI2)
+ Ins2Idx = LIS->InsertMachineInstrInMaps(*InsMI2);
+ SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
+ SlotIndex ExtIdx = LIS->InsertMachineInstrInMaps(*ExtMI);
+ LIS->getInterval(InRegLEA);
+ LIS->getInterval(OutRegLEA);
+ if (InRegLEA2)
+ LIS->getInterval(InRegLEA2);
+
+ // Move the use of Src up to InsMI.
+ LiveInterval &SrcLI = LIS->getInterval(Src);
+ LiveRange::Segment *SrcSeg = SrcLI.getSegmentContaining(NewIdx);
+ if (SrcSeg->end == NewIdx.getRegSlot())
+ SrcSeg->end = InsIdx.getRegSlot();
+
+ if (InsMI2) {
+ // Move the use of Src2 up to InsMI2.
+ LiveInterval &Src2LI = LIS->getInterval(Src2);
+ LiveRange::Segment *Src2Seg = Src2LI.getSegmentContaining(NewIdx);
+ if (Src2Seg->end == NewIdx.getRegSlot())
+ Src2Seg->end = Ins2Idx.getRegSlot();
+ }
+
+ // Move the definition of Dest down to ExtMI.
+ LiveInterval &DestLI = LIS->getInterval(Dest);
+ LiveRange::Segment *DestSeg =
+ DestLI.getSegmentContaining(NewIdx.getRegSlot());
+ assert(DestSeg->start == NewIdx.getRegSlot() &&
+ DestSeg->valno->def == NewIdx.getRegSlot());
+ DestSeg->start = ExtIdx.getRegSlot();
+ DestSeg->valno->def = ExtIdx.getRegSlot();
+ }
+
return ExtMI;
}
@@ -1381,7 +1435,8 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
/// performed, otherwise it returns the new instruction.
///
MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const {
+ LiveVariables *LV,
+ LiveIntervals *LIS) const {
// The following opcodes also sets the condition code register(s). Only
// convert them to equivalent lea if the condition code register def's
// are dead!
@@ -1404,6 +1459,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
return nullptr;
MachineInstr *NewMI = nullptr;
+ Register SrcReg, SrcReg2;
bool Is64Bit = Subtarget.is64Bit();
bool Is8BitOp = false;
@@ -1438,10 +1494,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
// LEA can't handle ESP.
bool isKill;
- Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
- if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
- SrcReg, isKill, ImplicitOp, LV))
+ if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
+ ImplicitOp, LV, LIS))
return nullptr;
MachineInstrBuilder MIB =
@@ -1466,7 +1521,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
unsigned ShAmt = getTruncatedShiftCount(MI, 2);
if (!isTruncatedShiftCountForLEA(ShAmt))
return nullptr;
- return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
+ return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
}
case X86::INC64r:
case X86::INC32r: {
@@ -1474,10 +1529,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
(Is64Bit ? X86::LEA64_32r : X86::LEA32r);
bool isKill;
- Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
- if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
- ImplicitOp, LV))
+ if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
+ ImplicitOp, LV, LIS))
return nullptr;
MachineInstrBuilder MIB =
@@ -1497,10 +1551,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
: (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
bool isKill;
- Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
- if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
- ImplicitOp, LV))
+ if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
+ ImplicitOp, LV, LIS))
return nullptr;
MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
@@ -1519,7 +1572,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
LLVM_FALLTHROUGH;
case X86::DEC16r:
case X86::INC16r:
- return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
+ return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
case X86::ADD64rr:
case X86::ADD64rr_DB:
case X86::ADD32rr:
@@ -1533,14 +1586,12 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
const MachineOperand &Src2 = MI.getOperand(2);
bool isKill2;
- Register SrcReg2;
MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
- if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
- SrcReg2, isKill2, ImplicitOp2, LV))
+ if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/false, SrcReg2, isKill2,
+ ImplicitOp2, LV, LIS))
return nullptr;
bool isKill;
- Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (Src.getReg() == Src2.getReg()) {
// Don't call classify LEAReg a second time on the same register, in case
@@ -1548,8 +1599,8 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
isKill = isKill2;
SrcReg = SrcReg2;
} else {
- if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true,
- SrcReg, isKill, ImplicitOp, LV))
+ if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
+ ImplicitOp, LV, LIS))
return nullptr;
}
@@ -1570,7 +1621,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
LLVM_FALLTHROUGH;
case X86::ADD16rr:
case X86::ADD16rr_DB:
- return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
+ return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
case X86::ADD64ri32:
case X86::ADD64ri8:
case X86::ADD64ri32_DB:
@@ -1588,10 +1639,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
bool isKill;
- Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
- if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
- SrcReg, isKill, ImplicitOp, LV))
+ if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
+ ImplicitOp, LV, LIS))
return nullptr;
MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
@@ -1611,7 +1661,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
case X86::ADD16ri8:
case X86::ADD16ri_DB:
case X86::ADD16ri8_DB:
- return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
+ return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
case X86::SUB8ri:
case X86::SUB16ri8:
case X86::SUB16ri:
@@ -1629,10 +1679,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
bool isKill;
- Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
- if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
- SrcReg, isKill, ImplicitOp, LV))
+ if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
+ ImplicitOp, LV, LIS))
return nullptr;
MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
@@ -1821,6 +1870,15 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
MachineBasicBlock &MBB = *MI.getParent();
MBB.insert(MI.getIterator(), NewMI); // Insert the new inst
+
+ if (LIS) {
+ LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
+ if (SrcReg)
+ LIS->getInterval(SrcReg);
+ if (SrcReg2)
+ LIS->getInterval(SrcReg2);
+ }
+
return NewMI;
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index b07e82b64277d..6b0a6c220b513 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -249,7 +249,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
bool &isKill, MachineOperand &ImplicitOp,
- LiveVariables *LV) const;
+ LiveVariables *LV, LiveIntervals *LIS) const;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
@@ -261,8 +261,8 @@ class X86InstrInfo final : public X86GenInstrInfo {
/// This method returns a null pointer if the transformation cannot be
/// performed, otherwise it returns the new instruction.
///
- MachineInstr *convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV) const override;
+ MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ LiveIntervals *LIS) const override;
/// Returns true iff the routine could find two commutable operands in the
/// given machine instruction.
@@ -589,9 +589,9 @@ class X86InstrInfo final : public X86GenInstrInfo {
/// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
/// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
/// super-register and then truncating back down to a 8/16-bit sub-register.
- MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
- MachineInstr &MI,
+ MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
LiveVariables *LV,
+ LiveIntervals *LIS,
bool Is8BitOp) const;
/// Handles memory folding for special case instructions, for instance those
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