[llvm] f7eb061 - [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 17 00:56:54 PST 2021
Author: Eric Tang
Date: 2021-11-17T08:55:11Z
New Revision: f7eb061a5f1ee8e357cb8a735f789719415eba66
URL: https://github.com/llvm/llvm-project/commit/f7eb061a5f1ee8e357cb8a735f789719415eba66
DIFF: https://github.com/llvm/llvm-project/commit/f7eb061a5f1ee8e357cb8a735f789719415eba66.diff
LOG: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors
This change make WidenVecRes_SELECT work for scalable vectors.
This patch is split from [D110319](https://reviews.llvm.org/D110319)
Signed-off-by: Eric Tang <tangxingxin1008 at gmail.com>
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D110388
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/test/CodeGen/AArch64/sve-pred-log.ll
llvm/test/CodeGen/AArch64/sve-select.ll
llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 6da8c3ced060f..539c9cb9c2561 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -4527,7 +4527,7 @@ SDValue DAGTypeLegalizer::WidenVSELECTMask(SDNode *N) {
SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
+ ElementCount WidenEC = WidenVT.getVectorElementCount();
SDValue Cond1 = N->getOperand(0);
EVT CondVT = Cond1.getValueType();
@@ -4541,8 +4541,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
}
EVT CondEltVT = CondVT.getVectorElementType();
- EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
- CondEltVT, WidenNumElts);
+ EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), CondEltVT, WidenEC);
if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
Cond1 = GetWidenedVector(Cond1);
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-log.ll b/llvm/test/CodeGen/AArch64/sve-pred-log.ll
index 7116ccf8acfad..a66375258db3a 100644
--- a/llvm/test/CodeGen/AArch64/sve-pred-log.ll
+++ b/llvm/test/CodeGen/AArch64/sve-pred-log.ll
@@ -32,6 +32,14 @@ define <vscale x 2 x i1> @vselect_2(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn
ret <vscale x 2 x i1> %res;
}
+define <vscale x 1 x i1> @vselect_1(<vscale x 1 x i1> %Pg, <vscale x 1 x i1> %Pn, <vscale x 1 x i1> %Pd) {
+; CHECK-LABEL: vselect_1:
+; CHECK: sel p0.b, p0, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = select <vscale x 1 x i1> %Pg, <vscale x 1 x i1> %Pn, <vscale x 1 x i1> %Pd
+ ret <vscale x 1 x i1> %res;
+}
+
define <vscale x 16 x i1> @and_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {
; CHECK-LABEL: and_16:
; CHECK: and p0.b, p0/z, p1.b, p2.b
diff --git a/llvm/test/CodeGen/AArch64/sve-select.ll b/llvm/test/CodeGen/AArch64/sve-select.ll
index 9f00eb6790ff7..819620a299f00 100644
--- a/llvm/test/CodeGen/AArch64/sve-select.ll
+++ b/llvm/test/CodeGen/AArch64/sve-select.ll
@@ -1,6 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
+define <vscale x 1 x i8> @select_nxv1i8(i1 %cond, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {
+; CHECK-LABEL: select_nxv1i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.b, xzr, x8
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b
+ ret <vscale x 1 x i8> %res
+}
+
define <vscale x 16 x i8> @select_nxv16i8(i1 %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: select_nxv16i8:
; CHECK: // %bb.0:
@@ -13,6 +25,18 @@ define <vscale x 16 x i8> @select_nxv16i8(i1 %cond, <vscale x 16 x i8> %a, <vs
ret <vscale x 16 x i8> %res
}
+define <vscale x 1 x i16> @select_nxv1i16(i1 %cond, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b) {
+; CHECK-LABEL: select_nxv1i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.h, xzr, x8
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b
+ ret <vscale x 1 x i16> %res
+}
+
define <vscale x 8 x i16> @select_nxv8i16(i1 %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: select_nxv8i16:
; CHECK: // %bb.0:
@@ -25,6 +49,18 @@ define <vscale x 8 x i16> @select_nxv8i16(i1 %cond, <vscale x 8 x i16> %a, <vs
ret <vscale x 8 x i16> %res
}
+define <vscale x 1 x i32> @select_nxv1i32(i1 %cond, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {
+; CHECK-LABEL: select_nxv1i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.s, xzr, x8
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b
+ ret <vscale x 1 x i32> %res
+}
+
define <vscale x 4 x i32> @select_nxv4i32(i1 %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: select_nxv4i32:
; CHECK: // %bb.0:
@@ -37,6 +73,18 @@ define <vscale x 4 x i32> @select_nxv4i32(i1 %cond, <vscale x 4 x i32> %a, <vs
ret <vscale x 4 x i32> %res
}
+define <vscale x 1 x i64> @select_nxv1i64(i1 %cond, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {
+; CHECK-LABEL: select_nxv1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.d, xzr, x8
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b
+ ret <vscale x 1 x i64> %res
+}
+
define <vscale x 2 x i64> @select_nxv2i64(i1 %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: select_nxv2i64:
; CHECK: // %bb.0:
@@ -133,6 +181,18 @@ define <vscale x 2 x i1> @select_nxv2i1(i1 %cond, <vscale x 2 x i1> %a, <vscal
ret <vscale x 2 x i1> %res
}
+define <vscale x 1 x i1> @select_nxv1i1(i1 %cond, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: select_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p2.d, xzr, x8
+; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b
+ ret <vscale x 1 x i1> %res
+}
+
; Integer vector select
define <vscale x 16 x i8> @sel_nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %dst, <vscale x 16 x i8> %a) {
@@ -162,6 +222,15 @@ define <vscale x 4 x i32> @sel_nxv4i32(<vscale x 4 x i1> %p, <vscale x 4 x i32>
ret <vscale x 4 x i32> %sel
}
+define <vscale x 1 x i64> @sel_nxv1i64(<vscale x 1 x i1> %p, <vscale x 1 x i64> %dst, <vscale x 1 x i64> %a) {
+; CHECK-LABEL: sel_nxv1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+ %sel = select <vscale x 1 x i1> %p, <vscale x 1 x i64> %a, <vscale x 1 x i64> %dst
+ ret <vscale x 1 x i64> %sel
+}
+
define <vscale x 2 x i64> @sel_nxv2i64(<vscale x 2 x i1> %p, <vscale x 2 x i64> %dst, <vscale x 2 x i64> %a) {
; CHECK-LABEL: sel_nxv2i64:
; CHECK: // %bb.0:
@@ -295,6 +364,20 @@ define <vscale x 8 x half> @icmp_select_nxv8f16(<vscale x 8 x half> %a, <vscale
ret <vscale x 8 x half> %sel
}
+define <vscale x 1 x i64> @icmp_select_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i64 %x0) {
+; CHECK-LABEL: icmp_select_nxv1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: cset w8, eq
+; CHECK-NEXT: sbfx x8, x8, #0, #1
+; CHECK-NEXT: whilelo p0.d, xzr, x8
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %mask = icmp eq i64 %x0, 0
+ %sel = select i1 %mask, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b
+ ret <vscale x 1 x i64> %sel
+}
+
define <vscale x 2 x i64> @icmp_select_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i64 %x0) {
; CHECK-LABEL: icmp_select_nxv2i64:
; CHECK: // %bb.0:
@@ -309,6 +392,20 @@ define <vscale x 2 x i64> @icmp_select_nxv2i64(<vscale x 2 x i64> %a, <vscale x
ret <vscale x 2 x i64> %sel
}
+define <vscale x 1 x i32> @icmp_select_nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i64 %x0) {
+; CHECK-LABEL: icmp_select_nxv1i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: cset w8, eq
+; CHECK-NEXT: sbfx x8, x8, #0, #1
+; CHECK-NEXT: whilelo p0.s, xzr, x8
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+ %mask = icmp eq i64 %x0, 0
+ %sel = select i1 %mask, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b
+ ret <vscale x 1 x i32> %sel
+}
+
define <vscale x 4 x i32> @icmp_select_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i64 %x0) {
; CHECK-LABEL: icmp_select_nxv4i32:
; CHECK: // %bb.0:
@@ -323,6 +420,20 @@ define <vscale x 4 x i32> @icmp_select_nxv4i32(<vscale x 4 x i32> %a, <vscale x
ret <vscale x 4 x i32> %sel
}
+define <vscale x 1 x i16> @icmp_select_nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i64 %x0) {
+; CHECK-LABEL: icmp_select_nxv1i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: cset w8, eq
+; CHECK-NEXT: sbfx x8, x8, #0, #1
+; CHECK-NEXT: whilelo p0.h, xzr, x8
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+ %mask = icmp eq i64 %x0, 0
+ %sel = select i1 %mask, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b
+ ret <vscale x 1 x i16> %sel
+}
+
define <vscale x 8 x i16> @icmp_select_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i64 %x0) {
; CHECK-LABEL: icmp_select_nxv8i16:
; CHECK: // %bb.0:
@@ -337,6 +448,20 @@ define <vscale x 8 x i16> @icmp_select_nxv8i16(<vscale x 8 x i16> %a, <vscale x
ret <vscale x 8 x i16> %sel
}
+define <vscale x 1 x i8> @icmp_select_nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i64 %x0) {
+; CHECK-LABEL: icmp_select_nxv1i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: cset w8, eq
+; CHECK-NEXT: sbfx x8, x8, #0, #1
+; CHECK-NEXT: whilelo p0.b, xzr, x8
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+ %mask = icmp eq i64 %x0, 0
+ %sel = select i1 %mask, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b
+ ret <vscale x 1 x i8> %sel
+}
+
define <vscale x 16 x i8> @icmp_select_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 %x0) {
; CHECK-LABEL: icmp_select_nxv16i8:
; CHECK: // %bb.0:
@@ -351,6 +476,20 @@ define <vscale x 16 x i8> @icmp_select_nxv16i8(<vscale x 16 x i8> %a, <vscale x
ret <vscale x 16 x i8> %sel
}
+define <vscale x 1 x i1> @icmp_select_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i64 %x0) {
+; CHECK-LABEL: icmp_select_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: cset w8, eq
+; CHECK-NEXT: sbfx x8, x8, #0, #1
+; CHECK-NEXT: whilelo p2.d, xzr, x8
+; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
+; CHECK-NEXT: ret
+ %mask = icmp eq i64 %x0, 0
+ %sel = select i1 %mask, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b
+ ret <vscale x 1 x i1> %sel
+}
+
define <vscale x 2 x i1> @icmp_select_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, i64 %x0) {
; CHECK-LABEL: icmp_select_nxv2i1:
; CHECK: // %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
index e9c53906b75d7..7df7112bb43be 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
@@ -69,6 +69,40 @@ define <vscale x 2 x i8> @vmerge_iv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x
ret <vscale x 2 x i8> %vc
}
+define <vscale x 3 x i8> @vmerge_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %cond) {
+; CHECK-LABEL: vmerge_vv_nxv3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
+; CHECK-NEXT: ret
+ %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %va, <vscale x 3 x i8> %vb
+ ret <vscale x 3 x i8> %vc
+}
+
+define <vscale x 3 x i8> @vmerge_xv_nxv3i8(<vscale x 3 x i8> %va, i8 signext %b, <vscale x 3 x i1> %cond) {
+; CHECK-LABEL: vmerge_xv_nxv3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 3 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> undef, <vscale x 3 x i32> zeroinitializer
+ %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %splat, <vscale x 3 x i8> %va
+ ret <vscale x 3 x i8> %vc
+}
+
+define <vscale x 3 x i8> @vmerge_iv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %cond) {
+; CHECK-LABEL: vmerge_iv_nxv3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vmerge.vim v8, v8, 3, v0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 3 x i8> undef, i8 3, i32 0
+ %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> undef, <vscale x 3 x i32> zeroinitializer
+ %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %splat, <vscale x 3 x i8> %va
+ ret <vscale x 3 x i8> %vc
+}
+
define <vscale x 4 x i8> @vmerge_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %cond) {
; CHECK-LABEL: vmerge_vv_nxv4i8:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll
index 491b36cc98d57..5c79b20c439b0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll
@@ -69,6 +69,40 @@ define <vscale x 2 x i8> @vmerge_iv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x
ret <vscale x 2 x i8> %vc
}
+define <vscale x 3 x i8> @vmerge_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %cond) {
+; CHECK-LABEL: vmerge_vv_nxv3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
+; CHECK-NEXT: ret
+ %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %va, <vscale x 3 x i8> %vb
+ ret <vscale x 3 x i8> %vc
+}
+
+define <vscale x 3 x i8> @vmerge_xv_nxv3i8(<vscale x 3 x i8> %va, i8 signext %b, <vscale x 3 x i1> %cond) {
+; CHECK-LABEL: vmerge_xv_nxv3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 3 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> undef, <vscale x 3 x i32> zeroinitializer
+ %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %splat, <vscale x 3 x i8> %va
+ ret <vscale x 3 x i8> %vc
+}
+
+define <vscale x 3 x i8> @vmerge_iv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %cond) {
+; CHECK-LABEL: vmerge_iv_nxv3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vmerge.vim v8, v8, 3, v0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 3 x i8> undef, i8 3, i32 0
+ %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> undef, <vscale x 3 x i32> zeroinitializer
+ %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %splat, <vscale x 3 x i8> %va
+ ret <vscale x 3 x i8> %vc
+}
+
define <vscale x 4 x i8> @vmerge_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %cond) {
; CHECK-LABEL: vmerge_vv_nxv4i8:
; CHECK: # %bb.0:
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