[PATCH] D113994: [AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot

[David Sherwood via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG460745902275: [AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering… (authored by david-arm).

Changed prior to commit:
  https://reviews.llvm.org/D113994?vs=387603&id=387657#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113994/new/

https://reviews.llvm.org/D113994

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/vselect-constants.ll


Index: llvm/test/CodeGen/AArch64/vselect-constants.ll
===================================================================
--- llvm/test/CodeGen/AArch64/vselect-constants.ll
+++ llvm/test/CodeGen/AArch64/vselect-constants.ll
@@ -363,3 +363,21 @@
   %r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer
   ret <2 x i64> %r
 }
+
+; SVE
+
+define <vscale x 16 x i8> @signbit_mask_xor_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
+; CHECK-LABEL: signbit_mask_xor_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.b
+; CHECK-NEXT:    cmplt p0.b, p0/z, z0.b, #0
+; CHECK-NEXT:    eor z0.d, z0.d, z1.d
+; CHECK-NEXT:    mov z0.b, p0/m, #0 // =0x0
+; CHECK-NEXT:    ret
+  %cond = icmp slt <vscale x 16 x i8> %a, zeroinitializer
+  %xor = xor <vscale x 16 x i8> %a, %b
+  %r = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %xor
+  ret <vscale x 16 x i8> %r
+}
+
+attributes #0 = { "target-features"="+sve" }
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -743,7 +743,9 @@
     if (!VT.isVector())
       return hasAndNotCompare(Y);
 
-    return VT.getSizeInBits() >= 64; // vector 'bic'
+    TypeSize TS = VT.getSizeInBits();
+    // TODO: We should be able to use bic/bif too for SVE.
+    return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
   }
 
   bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(


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