[llvm] 4607459 - [AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot

[David Sherwood via llvm-commits]

Author: David Sherwood
Date: 2021-11-16T16:25:16Z
New Revision: 460745902275c341889bde9daeb41287359e59e3

URL: https://github.com/llvm/llvm-project/commit/460745902275c341889bde9daeb41287359e59e3
DIFF: https://github.com/llvm/llvm-project/commit/460745902275c341889bde9daeb41287359e59e3.diff

LOG: [AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot

For now I've just changed the code to only return true from
AArch64ISelLowering::hasAndNot if the vector is fixed-length.
Once we have the right patterns or DAG combines to use bic/bif
we can also enable this for SVE.

Test added here:

  CodeGen/AArch64/vselect-constants.ll

Differential Revision: https://reviews.llvm.org/D113994

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.h
    llvm/test/CodeGen/AArch64/vselect-constants.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 2ddaa7431d03..392e22b68366 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -743,7 +743,9 @@ class AArch64TargetLowering : public TargetLowering {
     if (!VT.isVector())
       return hasAndNotCompare(Y);
 
-    return VT.getSizeInBits() >= 64; // vector 'bic'
+    TypeSize TS = VT.getSizeInBits();
+    // TODO: We should be able to use bic/bif too for SVE.
+    return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
   }
 
   bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(

diff  --git a/llvm/test/CodeGen/AArch64/vselect-constants.ll b/llvm/test/CodeGen/AArch64/vselect-constants.ll
index 332d11029c16..a11662fea7a5 100644
--- a/llvm/test/CodeGen/AArch64/vselect-constants.ll
+++ b/llvm/test/CodeGen/AArch64/vselect-constants.ll
@@ -363,3 +363,21 @@ define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {
   %r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer
   ret <2 x i64> %r
 }
+
+; SVE
+
+define <vscale x 16 x i8> @signbit_mask_xor_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
+; CHECK-LABEL: signbit_mask_xor_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.b
+; CHECK-NEXT:    cmplt p0.b, p0/z, z0.b, #0
+; CHECK-NEXT:    eor z0.d, z0.d, z1.d
+; CHECK-NEXT:    mov z0.b, p0/m, #0 // =0x0
+; CHECK-NEXT:    ret
+  %cond = icmp slt <vscale x 16 x i8> %a, zeroinitializer
+  %xor = xor <vscale x 16 x i8> %a, %b
+  %r = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %xor
+  ret <vscale x 16 x i8> %r
+}
+
+attributes #0 = { "target-features"="+sve" }