[PATCH] D113970: [SelectionDAG] Add pattern to haveNoCommonBitsSet.

[Omer Aviram via Phabricator via llvm-commits]

OmerAviram created this revision.
OmerAviram added reviewers: RKSimon, spatel, lebedev.ri.
Herald added subscribers: ecnelises, hiraditya.
OmerAviram requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Correctly identify the following pattern, which has no common bits: (X & ~M) op (Y & M).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113970

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4539,11 +4539,28 @@
   return false;
 }
 
+static bool matchNoCommonBitsPattern(SDValue A, SDValue B) {
+  if (isBitwiseNot(A, true)) {
+    SDValue NotOperand = A->getOperand(0);
+    assert(B->getOpcode() == ISD::AND && "Expected AND opcode!");
+    if (NotOperand == B->getOperand(0) || NotOperand == B->getOperand(1))
+      return true;
+  }
+  return false;
+}
+
 // FIXME: unify with llvm::haveNoCommonBitsSet.
-// FIXME: could also handle masked merge pattern (X & ~M) op (Y & M)
 bool SelectionDAG::haveNoCommonBitsSet(SDValue A, SDValue B) const {
   assert(A.getValueType() == B.getValueType() &&
          "Values must have the same type");
+  // Match masked merge pattern (X & ~M) op (Y & M)
+  if (A->getOpcode() == ISD::AND && B->getOpcode() == ISD::AND) {
+    if (matchNoCommonBitsPattern(A->getOperand(0), B) ||
+        matchNoCommonBitsPattern(A->getOperand(1), B) ||
+        matchNoCommonBitsPattern(B->getOperand(0), A) ||
+        matchNoCommonBitsPattern(B->getOperand(1), A))
+      return true;
+  }
   return KnownBits::haveNoCommonBitsSet(computeKnownBits(A),
                                         computeKnownBits(B));
 }


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