[PATCH] D113960: PrologEpilogInserter: Use explicit control for scavenge slot placement

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: thegameg, MatzeB, qcolombet, rampitec, rsandifo, rsandifo-arm, uweigand.
Herald added subscribers: foad, kerbowa, atanasyan, jrtc27, hiraditya, tpr, nhaehnle, jvesely, sdardis.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

AMDGPU is unusual in that the both stack is indexed in the same
direction as stack growth (up). We therefore always need the emergency
stack slots placed as low as possible to ensure they are in range of
load/store instruction immediate offsets. The existing logic is mostly
OK, but failed if we required stack realignment.

      

I don't understand what the existing control isFPCloseToIncomingSP is
supposed to mean, but can only be used to stop placing the scavenge
slots earlier. Make this explicit so that targets can opt-in rather
than opt-out only.


https://reviews.llvm.org/D113960

Files:
  llvm/include/llvm/CodeGen/TargetFrameLowering.h
  llvm/lib/CodeGen/PrologEpilogInserter.cpp
  llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.h
  llvm/lib/Target/Mips/MipsFrameLowering.h
  llvm/lib/Target/SystemZ/SystemZFrameLowering.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
  llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch.ll
  llvm/test/CodeGen/AMDGPU/load-hi16.ll
  llvm/test/CodeGen/AMDGPU/load-lo16.ll
  llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
  llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
  llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
  llvm/test/CodeGen/AMDGPU/store-hi16.ll

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