[PATCH] D113913: [X86][Costmodel] `trunc v32i16 to v64i1` can appear after legalization, cost is same as for `trunc v32i16 to v32i1`

Mon Nov 15 09:59:19 PST 2021

lebedev.ri created this revision.
lebedev.ri added a reviewer: RKSimon.
lebedev.ri added a project: LLVM.
Herald added subscribers: pengfei, hiraditya.
lebedev.ri requested review of this revision.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113913

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
  llvm/test/Analysis/CostModel/X86/trunc.ll


Index: llvm/test/Analysis/CostModel/X86/trunc.ll
===================================================================

--- llvm/test/Analysis/CostModel/X86/trunc.ll
+++ llvm/test/Analysis/CostModel/X86/trunc.ll
@@ -2467,25 +2467,25 @@
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V24i16 = trunc <24 x i16> undef to <24 x i1>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V28i16 = trunc <28 x i16> undef to <28 x i1>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 80 for instruction: %V40i16 = trunc <40 x i16> undef to <40 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V48i16 = trunc <48 x i16> undef to <48 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 112 for instruction: %V56i16 = trunc <56 x i16> undef to <56 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 160 for instruction: %V80i16 = trunc <80 x i16> undef to <80 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 224 for instruction: %V112i16 = trunc <112 x i16> undef to <112 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V128i16 = trunc <128 x i16> undef to <128 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 320 for instruction: %V160i16 = trunc <160 x i16> undef to <160 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 384 for instruction: %V192i16 = trunc <192 x i16> undef to <192 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 448 for instruction: %V224i16 = trunc <224 x i16> undef to <224 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V256i16 = trunc <256 x i16> undef to <256 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 640 for instruction: %V320i16 = trunc <320 x i16> undef to <320 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 768 for instruction: %V384i16 = trunc <384 x i16> undef to <384 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 896 for instruction: %V448i16 = trunc <448 x i16> undef to <448 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 40 for instruction: %V512i16 = trunc <512 x i16> undef to <512 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1280 for instruction: %V640i16 = trunc <640 x i16> undef to <640 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1536 for instruction: %V768i16 = trunc <768 x i16> undef to <768 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1792 for instruction: %V896i16 = trunc <896 x i16> undef to <896 x i1>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 80 for instruction: %V1024i16 = trunc <1024 x i16> undef to <1024 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V40i16 = trunc <40 x i16> undef to <40 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V48i16 = trunc <48 x i16> undef to <48 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V56i16 = trunc <56 x i16> undef to <56 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V80i16 = trunc <80 x i16> undef to <80 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V112i16 = trunc <112 x i16> undef to <112 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V128i16 = trunc <128 x i16> undef to <128 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V160i16 = trunc <160 x i16> undef to <160 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V192i16 = trunc <192 x i16> undef to <192 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V224i16 = trunc <224 x i16> undef to <224 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V256i16 = trunc <256 x i16> undef to <256 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V320i16 = trunc <320 x i16> undef to <320 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V384i16 = trunc <384 x i16> undef to <384 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V448i16 = trunc <448 x i16> undef to <448 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V512i16 = trunc <512 x i16> undef to <512 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V640i16 = trunc <640 x i16> undef to <640 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V768i16 = trunc <768 x i16> undef to <768 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V896i16 = trunc <896 x i16> undef to <896 x i1>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V1024i16 = trunc <1024 x i16> undef to <1024 x i1>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %i8 = trunc i8 undef to i1
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V2i8 = trunc <2 x i8> undef to <2 x i1>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V3i8 = trunc <3 x i8> undef to <3 x i1>
Index: llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
+++ llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
@@ -663,7 +663,7 @@
 ; SKX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V8i16 = trunc <8 x i16> undef to <8 x i1>
 ; SKX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V16i16 = trunc <16 x i16> undef to <16 x i1>
 ; SKX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i1>
-; SKX512-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1>
+; SKX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1>
 ; SKX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V2i8 = trunc <2 x i8> undef to <2 x i1>
 ; SKX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V4i8 = trunc <4 x i8> undef to <4 x i1>
 ; SKX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V8i8 = trunc <8 x i8> undef to <8 x i1>
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -1624,6 +1624,7 @@
     { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i16, 2 }, // widen to zmm
     { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i8,  2 }, // widen to zmm
     { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i16, 2 },
+    { ISD::TRUNCATE,    MVT::v64i1,  MVT::v32i16, 2 },
     { ISD::TRUNCATE,    MVT::v64i1,  MVT::v64i8,  2 },
   };
 


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