[PATCH] D111362: [PowerPC] Add support for ROP protection for 32 bit.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp marked an inline comment as not done.
stefanp added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:5486
+// specified address.
+let mayLoad = 1, hasSideEffects = 1, isCodeGenOnly = 1 in {
+def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs),
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nemanjai wrote:
> stefanp wrote:
> > amyk wrote:
> > > Just wanted to double check that `isCodeGenOnly` is intended for these, right? 
> > > I don't have a strong opinion either way but since they're not on the 64-bit version and since `hasSideEffects` is documented, it may not hurt to document why `isCodeGenOnly` is added here.
> > Sure. I can add that.
> > The idea is that we don't want the llvm to get confused between HASHCHK and HASHCHK8 because they are both encoded the same way. I'll add a comment with an explanation. 
> I think Amy's question is why this one parts with the convention to make the 32-bit versions the real instructions and the 64-bit version the `isCodeGenOnly` instruction (along with being marked with `Interpretation64Bit`). And I think the question is perfectly reasonable.
Oh I see what you mean. I'm sorry I think I misunderstood initially. There is no reason why I did it this way. I will switch the flags so that the `isCodeGenOnly` flag is on the 64 bit version.


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  https://reviews.llvm.org/D111362/new/

https://reviews.llvm.org/D111362