[PATCH] D113890: [RISCV] Add new ELF attribute to track reserved registers

[Edward Jones via Phabricator via llvm-commits]

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This attribute is described in this pull request to the RISCV psABI: New attribute: Tag_RISCV_reserved_register <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/195>

This adds a new attribute used to record reserved register information. This is used to check compatibility between ABI subvariants like overlay which reserve registers for use in the overlay engine.

Currently this is limited to only the x0-x31 range of registers. At the very least support for the floating point registers needs to be added, and in future this may also need to handle registers outside the available 64 bit mask (eg CSR or vector extension registers)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113890

Files:
  llvm/include/llvm/MC/MCELFStreamer.h
  llvm/include/llvm/Support/ELFAttributeParser.h
  llvm/include/llvm/Support/RISCVAttributes.h
  llvm/lib/MC/MCELFStreamer.cpp
  llvm/lib/Support/ELFAttributeParser.cpp
  llvm/lib/Support/RISCVAttributeParser.cpp
  llvm/lib/Support/RISCVAttributes.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-reserved-regs.s
  llvm/test/MC/RISCV/attribute.s

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