[PATCH] D113475: [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu added inline comments.


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Comment at: llvm/include/llvm/Target/Target.td:663-674
+/// Defines a Pat match between compressed and uncompressed instruction.
+/// The relationship and helper function generation are handled by
+/// CompressInstEmitter backend.
+class CompressPat<dag input, dag output, list<Predicate> predicates = []> {
+  /// Uncompressed instruction description.
+  dag Input = input;
+  /// Compressed instruction description.
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jrtc27 wrote:
> Most of these comments don't make sense to me. Especially isCompressOnly's.
Anymore specific suggestion?


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  https://reviews.llvm.org/D113475/new/

https://reviews.llvm.org/D113475