[llvm] e49fcfc - [X86][ABI] Change the alignment of f80 in 32-bit calling convention to meet with different data layout
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 12 18:00:40 PST 2021
Author: Phoebe Wang
Date: 2021-11-13T10:00:34+08:00
New Revision: e49fcfc7cdf82e41f15a857083c0fb275c1b6021
URL: https://github.com/llvm/llvm-project/commit/e49fcfc7cdf82e41f15a857083c0fb275c1b6021
DIFF: https://github.com/llvm/llvm-project/commit/e49fcfc7cdf82e41f15a857083c0fb275c1b6021.diff
LOG: [X86][ABI] Change the alignment of f80 in 32-bit calling convention to meet with different data layout
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D113739
Added:
Modified:
llvm/lib/Target/X86/X86CallingConv.td
llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
llvm/test/CodeGen/X86/inline-asm-fpstack.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86CallingConv.td b/llvm/lib/Target/X86/X86CallingConv.td
index 63757ccc20a93..9bf621355d0a3 100644
--- a/llvm/lib/Target/X86/X86CallingConv.td
+++ b/llvm/lib/Target/X86/X86CallingConv.td
@@ -862,8 +862,8 @@ def CC_X86_32_Common : CallingConv<[
// Doubles get 8-byte slots that are 4-byte aligned.
CCIfType<[f64], CCAssignToStack<8, 4>>,
- // Long doubles get slots whose size depends on the subtarget.
- CCIfType<[f80], CCAssignToStack<0, 4>>,
+ // Long doubles get slots whose size and alignment depends on the subtarget.
+ CCIfType<[f80], CCAssignToStack<0, 0>>,
// Boolean vectors of AVX-512 are passed in SIMD registers.
// The call from AVX to AVX-512 function should work,
diff --git a/llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll b/llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
index 3ad6492978438..2cf09a936f592 100644
--- a/llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
+++ b/llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
@@ -8,8 +8,9 @@ entry:
ret x86_fp80 %tmp2
; CHECK-LABEL: foo:
-; CHECK: fldt 4(%esp)
+; CHECK: fldt 16(%esp)
; CHECK-NEXT: fsqrt
+; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: ret
}
@@ -20,10 +21,11 @@ entry:
%tmp2 = call x86_fp80 @llvm.powi.f80.i32( x86_fp80 %x, i32 3 )
ret x86_fp80 %tmp2
; CHECK-LABEL: bar:
-; CHECK: fldt 4(%esp)
+; CHECK: fldt 16(%esp)
; CHECK-NEXT: fld %st(0)
; CHECK-NEXT: fmul %st(1)
; CHECK-NEXT: fmulp
+; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: ret
}
diff --git a/llvm/test/CodeGen/X86/inline-asm-fpstack.ll b/llvm/test/CodeGen/X86/inline-asm-fpstack.ll
index 09f511454700e..757f259d99b45 100644
--- a/llvm/test/CodeGen/X86/inline-asm-fpstack.ll
+++ b/llvm/test/CodeGen/X86/inline-asm-fpstack.ll
@@ -29,10 +29,12 @@ define double @test2() nounwind {
define void @test3(x86_fp80 %X) nounwind {
; CHECK-LABEL: test3:
; CHECK: ## %bb.0:
+; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: frob
; CHECK-NEXT: ## InlineAsm End
+; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( x86_fp80 %X)
ret void
@@ -246,12 +248,14 @@ entry:
define void @fist1(x86_fp80 %x, i32* %p) nounwind ssp {
; CHECK-LABEL: fist1:
; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: fistl (%eax)
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
entry:
tail call void asm sideeffect "fistl $1", "{st},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind
@@ -269,11 +273,13 @@ entry:
define x86_fp80 @fist2(x86_fp80 %x, i32* %p) nounwind ssp {
; CHECK-LABEL: fist2:
; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: fistl (%eax)
; CHECK-NEXT: ## InlineAsm End
+; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
entry:
%0 = tail call x86_fp80 asm "fistl $2", "=&{st},0,*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind
@@ -288,6 +294,7 @@ entry:
define void @fucomp1(x86_fp80 %x, x86_fp80 %y) nounwind ssp {
; CHECK-LABEL: fucomp1:
; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fxch %st(1)
@@ -295,6 +302,7 @@ define void @fucomp1(x86_fp80 %x, x86_fp80 %y) nounwind ssp {
; CHECK-NEXT: fucomp %st(1)
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
entry:
tail call void asm sideeffect "fucomp $1", "{st},f,~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind
@@ -314,6 +322,7 @@ entry:
define void @fucomp2(x86_fp80 %x, x86_fp80 %y) nounwind ssp {
; CHECK-LABEL: fucomp2:
; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fxch %st(1)
@@ -321,6 +330,7 @@ define void @fucomp2(x86_fp80 %x, x86_fp80 %y) nounwind ssp {
; CHECK-NEXT: fucomp %st(1)
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
entry:
tail call void asm sideeffect "fucomp $1", "{st},{st(1)},~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind
@@ -330,12 +340,14 @@ entry:
define void @fucomp3(x86_fp80 %x, x86_fp80 %y) nounwind ssp {
; CHECK-LABEL: fucomp3:
; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: fucompp %st(1)
; CHECK-NEXT: ## InlineAsm End
+; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
entry:
tail call void asm sideeffect "fucompp $1", "{st},{st(1)},~{st},~{st(1)},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind
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