[llvm] 8909dc5 - [RISCV] Fixed duplicate RUN line on float-intrinsics.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 12 16:27:54 PST 2021
Author: Craig Topper
Date: 2021-11-12T16:27:36-08:00
New Revision: 8909dc5ebe8ad39f1743131eb70df402d796acab
URL: https://github.com/llvm/llvm-project/commit/8909dc5ebe8ad39f1743131eb70df402d796acab
DIFF: https://github.com/llvm/llvm-project/commit/8909dc5ebe8ad39f1743131eb70df402d796acab.diff
LOG: [RISCV] Fixed duplicate RUN line on float-intrinsics.ll. NFC
We had two identical RV64I RUN lines. One should be RV32I.
Added:
Modified:
llvm/test/CodeGen/RISCV/float-intrinsics.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
index e5b2ce6ea996..13cb256d8cef 100644
--- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -7,8 +7,8 @@
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
-; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
+; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
@@ -29,6 +29,15 @@ define float @sqrt_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: sqrt_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call sqrtf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: sqrt_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -63,6 +72,15 @@ define float @powi_f32(float %a, i32 %b) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: powi_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __powisf2 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: powi_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -97,6 +115,15 @@ define float @sin_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: sin_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call sinf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: sin_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -130,6 +157,15 @@ define float @cos_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: cos_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call cosf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: cos_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -184,6 +220,26 @@ define float @sincos_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: sincos_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: call sinf at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call cosf at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: sincos_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
@@ -230,6 +286,15 @@ define float @pow_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: pow_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call powf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: pow_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -263,6 +328,15 @@ define float @exp_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: exp_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call expf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: exp_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -296,6 +370,15 @@ define float @exp2_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: exp2_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call exp2f at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: exp2_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -329,6 +412,15 @@ define float @log_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: log_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call logf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: log_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -362,6 +454,15 @@ define float @log10_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: log10_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call log10f at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: log10_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -395,6 +496,15 @@ define float @log2_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: log2_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call log2f at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: log2_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -428,6 +538,15 @@ define float @fma_f32(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: fma_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: fma_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -461,6 +580,20 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: fmuladd_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: fmuladd_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -495,6 +628,13 @@ define float @fabs_f32(float %a) nounwind {
; RV64IF-NEXT: and a0, a0, a1
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: fabs_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: fabs_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 524288
@@ -524,6 +664,15 @@ define float @minnum_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: minnum_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fminf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: minnum_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -555,6 +704,15 @@ define float @maxnum_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: maxnum_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fmaxf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: maxnum_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -603,6 +761,15 @@ define float @copysign_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: copysign_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: copysign_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 524288
@@ -636,6 +803,15 @@ define float @floor_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: floor_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call floorf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: floor_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -669,6 +845,15 @@ define float @ceil_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: ceil_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call ceilf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: ceil_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -702,6 +887,15 @@ define float @trunc_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: trunc_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call truncf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: trunc_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -735,6 +929,15 @@ define float @rint_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: rint_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call rintf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: rint_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -768,6 +971,15 @@ define float @nearbyint_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: nearbyint_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call nearbyintf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: nearbyint_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -801,6 +1013,15 @@ define float @round_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: round_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call roundf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: round_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -834,6 +1055,15 @@ define float @roundeven_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: roundeven_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call roundevenf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: roundeven_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -861,6 +1091,15 @@ define iXLen @lrint_f32(float %a) nounwind {
; RV64IF-NEXT: fcvt.l.s a0, ft0
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: lrint_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call lrintf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: lrint_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -888,6 +1127,15 @@ define iXLen @lround_f32(float %a) nounwind {
; RV64IF-NEXT: fcvt.l.s a0, ft0, rmm
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: lround_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call lroundf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: lround_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -918,6 +1166,15 @@ define i64 @llrint_f32(float %a) nounwind {
; RV64IF-NEXT: fcvt.l.s a0, ft0
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: llrint_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call llrintf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: llrint_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -948,6 +1205,15 @@ define i64 @llround_f32(float %a) nounwind {
; RV64IF-NEXT: fcvt.l.s a0, ft0, rmm
; RV64IF-NEXT: ret
;
+; RV32I-LABEL: llround_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call llroundf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: llround_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
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