[PATCH] D111531: Fix minor deficiency in MachineSink.

[Markus Lavin via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4e94e25c9024: Fix minor deficiency in machine-sink. (authored by markus).

Changed prior to commit:
  https://reviews.llvm.org/D111531?vs=378604&id=386740#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111531/new/

https://reviews.llvm.org/D111531

Files:
  llvm/lib/CodeGen/MachineSink.cpp
  llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir


Index: llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
@@ -0,0 +1,33 @@
+# RUN: llc -mtriple=riscv32 %s -run-pass=machine-sink -o - | FileCheck %s
+
+# Verify that sinking of '%20:gpr = LUI 1, implicit $x0' is not inhibited by
+# the implicit use of '$x0'.
+# Register '$x0' is a 'MRI->isConstantPhysReg()' on RISCV and such uses should
+# not inhibit sinking transformation even though they are livein to the block
+# they are to be sunk into (inhibit under such conditions should only happen
+# for defines).
+
+---
+name:            f
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: bb.1:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT:   liveins: $x0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[LUI:%[0-9]+]]:gpr = LUI 1, implicit $x0
+  bb.0:
+    liveins: $x10
+    %10:gpr = COPY $x10
+    %20:gpr = LUI 1, implicit $x0
+    BEQ %10, %10, %bb.2
+    PseudoBR %bb.1
+  bb.1:
+    liveins: $x0
+    %30:gpr = ADDI %20, 5
+    PseudoBR %bb.3
+  bb.2:
+    PseudoBR %bb.3
+  bb.3:
+    PseudoRET
+...
Index: llvm/lib/CodeGen/MachineSink.cpp
===================================================================
--- llvm/lib/CodeGen/MachineSink.cpp
+++ llvm/lib/CodeGen/MachineSink.cpp
@@ -1324,7 +1324,8 @@
   // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
   for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
     const MachineOperand &MO = MI.getOperand(I);
-    if (!MO.isReg()) continue;
+    if (!MO.isReg() || MO.isUse())
+      continue;
     Register Reg = MO.getReg();
     if (Reg == 0 || !Register::isPhysicalRegister(Reg))
       continue;


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