[llvm] eb44f3f - [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 11 10:56:39 PST 2021
Author: Craig Topper
Date: 2021-11-11T10:56:27-08:00
New Revision: eb44f3fc584b3c00c96b045851e2cf0a78e96e21
URL: https://github.com/llvm/llvm-project/commit/eb44f3fc584b3c00c96b045851e2cf0a78e96e21
DIFF: https://github.com/llvm/llvm-project/commit/eb44f3fc584b3c00c96b045851e2cf0a78e96e21.diff
LOG: [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
This improves our coverage of soft float libcalls lowering.
Remove most of the test cases from rv64i-single-softfloat.ll. They
were duplicated in the test files that now test softflow. Only
a couple test cases for constrained FP remain. Those should be
removed when we start supporting constrained FP.
This is follow up from D113528.
Added:
Modified:
llvm/test/CodeGen/RISCV/double-arith.ll
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/double-fcmp.ll
llvm/test/CodeGen/RISCV/double-intrinsics.ll
llvm/test/CodeGen/RISCV/float-arith.ll
llvm/test/CodeGen/RISCV/float-convert.ll
llvm/test/CodeGen/RISCV/float-fcmp.ll
llvm/test/CodeGen/RISCV/float-frem.ll
llvm/test/CodeGen/RISCV/float-intrinsics.ll
llvm/test/CodeGen/RISCV/half-arith.ll
llvm/test/CodeGen/RISCV/half-convert.ll
llvm/test/CodeGen/RISCV/half-fcmp.ll
llvm/test/CodeGen/RISCV/half-intrinsics.ll
llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll
index e33d2e473658..d1ed1d270c75 100644
--- a/llvm/test/CodeGen/RISCV/double-arith.ll
+++ b/llvm/test/CodeGen/RISCV/double-arith.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
; These tests are each targeted at a particular RISC-V FPU instruction. Most
; other files in this folder exercise LLVM IR instructions that don't directly
@@ -32,6 +36,24 @@ define double @fadd_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fadd_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fadd_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fadd double %a, %b
ret double %1
}
@@ -60,6 +82,24 @@ define double @fsub_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fsub.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fsub_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __subdf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsub_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __subdf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fsub double %a, %b
ret double %1
}
@@ -88,6 +128,24 @@ define double @fmul_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmul.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fmul_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __muldf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmul_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __muldf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fmul double %a, %b
ret double %1
}
@@ -116,6 +174,24 @@ define double @fdiv_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fdiv.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fdiv_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __divdf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fdiv_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __divdf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fdiv double %a, %b
ret double %1
}
@@ -142,6 +218,24 @@ define double @fsqrt_d(double %a) nounwind {
; RV64IFD-NEXT: fsqrt.d ft0, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fsqrt_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call sqrt at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsqrt_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call sqrt at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.sqrt.f64(double %a)
ret double %1
}
@@ -172,6 +266,25 @@ define double @fsgnj_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fsgnj.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fsgnj_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: and a3, a3, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsgnj_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a2, zero, -1
+; RV64I-NEXT: slli a3, a2, 63
+; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: srli a2, a2, 1
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
%1 = call double @llvm.copysign.f64(double %a, double %b)
ret double %1
}
@@ -198,6 +311,37 @@ define i32 @fneg_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fneg.d ft1, ft0
; RV64IFD-NEXT: feq.d a0, ft0, ft1
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fneg_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a3, a1
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: xor a3, a1, a2
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: call __eqdf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fneg_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a1, a1, 63
+; RV64I-NEXT: xor a1, a0, a1
+; RV64I-NEXT: call __eqdf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fadd double %a, %a
%2 = fneg double %1
%3 = fcmp oeq double %1, %2
@@ -235,6 +379,27 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fsgnj.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fsgnjn_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: not a2, a3
+; RV32I-NEXT: lui a3, 524288
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: and a1, a1, a3
+; RV32I-NEXT: or a1, a1, a2
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsgnjn_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: not a1, a1
+; RV64I-NEXT: addi a2, zero, -1
+; RV64I-NEXT: slli a3, a2, 63
+; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: srli a2, a2, 1
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
%1 = fsub double -0.0, %b
%2 = call double @llvm.copysign.f64(double %a, double %1)
ret double %2
@@ -272,6 +437,35 @@ define double @fabs_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fabs_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv a3, a1
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a1, a3, a1
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fabs_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: addi a0, zero, -1
+; RV64I-NEXT: srli a0, a0, 1
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fadd double %a, %b
%2 = call double @llvm.fabs.f64(double %1)
%3 = fadd double %2, %1
@@ -304,6 +498,24 @@ define double @fmin_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmin.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fmin_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fmin at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmin_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fmin at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.minnum.f64(double %a, double %b)
ret double %1
}
@@ -334,6 +546,24 @@ define double @fmax_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmax.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fmax_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fmax at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmax_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fmax at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.maxnum.f64(double %a, double %b)
ret double %1
}
@@ -358,6 +588,26 @@ define i32 @feq_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: feq_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __eqdf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: feq_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __eqdf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp oeq double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -383,6 +633,26 @@ define i32 @flt_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: flt_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __ltdf2 at plt
+; RV32I-NEXT: slti a0, a0, 0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: flt_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __ltdf2 at plt
+; RV64I-NEXT: slti a0, a0, 0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp olt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -408,6 +678,26 @@ define i32 @fle_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fle_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __ledf2 at plt
+; RV32I-NEXT: slti a0, a0, 1
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fle_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __ledf2 at plt
+; RV64I-NEXT: slti a0, a0, 1
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ole double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -443,6 +733,24 @@ define double @fmadd_d(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fmadd_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fma at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmadd_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fma at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.fma.f64(double %a, double %b, double %c)
ret double %1
}
@@ -479,6 +787,62 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fmsub.d ft0, ft1, ft0, ft2
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fmsub_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a3
+; RV32I-NEXT: mv s3, a2
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, a4
+; RV32I-NEXT: mv a1, a5
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv a4, a0
+; RV32I-NEXT: lui a0, 524288
+; RV32I-NEXT: xor a5, a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a3, s2
+; RV32I-NEXT: call fma at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmsub_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a1, a1, 63
+; RV64I-NEXT: xor a2, a0, a1
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call fma at plt
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%c_ = fadd double 0.0, %c ; avoid negation using xor
%negc = fsub double -0.0, %c_
%1 = call double @llvm.fma.f64(double %a, double %b, double %negc)
@@ -519,6 +883,78 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fnmadd.d ft0, ft2, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fnmadd_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s4, a5
+; RV32I-NEXT: mv s5, a4
+; RV32I-NEXT: mv s2, a3
+; RV32I-NEXT: mv s3, a2
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv a0, s5
+; RV32I-NEXT: mv a1, s4
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv a4, a0
+; RV32I-NEXT: lui a0, 524288
+; RV32I-NEXT: xor a2, s1, a0
+; RV32I-NEXT: xor a5, a1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, a2
+; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a3, s2
+; RV32I-NEXT: call fma at plt
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmadd_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a2, a1, 63
+; RV64I-NEXT: xor a1, s1, a2
+; RV64I-NEXT: xor a2, a0, a2
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: mv a1, s2
+; RV64I-NEXT: call fma at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%a_ = fadd double 0.0, %a
%c_ = fadd double 0.0, %c
%nega = fsub double -0.0, %a_
@@ -561,6 +997,79 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fnmadd.d ft0, ft2, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fnmadd_d_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s4, a5
+; RV32I-NEXT: mv s1, a4
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: mv a1, a3
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv s5, a0
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s4
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv a4, a0
+; RV32I-NEXT: lui a0, 524288
+; RV32I-NEXT: xor a3, s0, a0
+; RV32I-NEXT: xor a5, a1, a0
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: mv a2, s5
+; RV32I-NEXT: call fma at plt
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmadd_d_2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a2, a1, 63
+; RV64I-NEXT: xor a1, s1, a2
+; RV64I-NEXT: xor a2, a0, a2
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: call fma at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%b_ = fadd double 0.0, %b
%c_ = fadd double 0.0, %c
%negb = fsub double -0.0, %b_
@@ -601,6 +1110,58 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fnmsub_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a5
+; RV32I-NEXT: mv s3, a4
+; RV32I-NEXT: mv s0, a3
+; RV32I-NEXT: mv s1, a2
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: mv a2, s1
+; RV32I-NEXT: mv a3, s0
+; RV32I-NEXT: mv a4, s3
+; RV32I-NEXT: mv a5, s2
+; RV32I-NEXT: call fma at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmsub_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a1, a1, 63
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: mv a1, s1
+; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: call fma at plt
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%a_ = fadd double 0.0, %a
%nega = fsub double -0.0, %a_
%1 = call double @llvm.fma.f64(double %nega, double %b, double %c)
@@ -639,6 +1200,62 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fnmsub_d_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a5
+; RV32I-NEXT: mv s3, a4
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: mv a1, a3
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: lui a0, 524288
+; RV32I-NEXT: xor a3, a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: mv a4, s3
+; RV32I-NEXT: mv a5, s2
+; RV32I-NEXT: call fma at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmsub_d_2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a1, a1, 63
+; RV64I-NEXT: xor a1, a0, a1
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: call fma at plt
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%b_ = fadd double 0.0, %b
%negb = fsub double -0.0, %b_
%1 = call double @llvm.fma.f64(double %a, double %negb, double %c)
@@ -673,6 +1290,38 @@ define double @fmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fmadd_d_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a5
+; RV32I-NEXT: mv s1, a4
+; RV32I-NEXT: call __muldf3 at plt
+; RV32I-NEXT: mv a2, s1
+; RV32I-NEXT: mv a3, s0
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmadd_d_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: call __muldf3 at plt
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fmul contract double %a, %b
%2 = fadd contract double %1, %c
ret double %2
@@ -710,6 +1359,70 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fmsub.d ft0, ft1, ft0, ft2
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fmsub_d_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a3
+; RV32I-NEXT: mv s3, a2
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, a4
+; RV32I-NEXT: mv a1, a5
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s5, a1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a3, s2
+; RV32I-NEXT: call __muldf3 at plt
+; RV32I-NEXT: mv a2, s4
+; RV32I-NEXT: mv a3, s5
+; RV32I-NEXT: call __subdf3 at plt
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmsub_d_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, s2
+; RV64I-NEXT: call __muldf3 at plt
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __subdf3 at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%c_ = fadd double 0.0, %c ; avoid negation using xor
%1 = fmul contract double %a, %b
%2 = fsub contract double %1, %c_
@@ -752,6 +1465,96 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fnmadd.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fnmadd_d_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a5
+; RV32I-NEXT: mv s3, a4
+; RV32I-NEXT: mv s0, a3
+; RV32I-NEXT: mv s1, a2
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s5, a1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv a0, s4
+; RV32I-NEXT: mv a1, s5
+; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a3, s1
+; RV32I-NEXT: call __muldf3 at plt
+; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: mv a2, s2
+; RV32I-NEXT: mv a3, s3
+; RV32I-NEXT: call __subdf3 at plt
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmadd_d_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a0, s3
+; RV64I-NEXT: mv a1, s1
+; RV64I-NEXT: call __muldf3 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a1, a1, 63
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __subdf3 at plt
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%a_ = fadd double 0.0, %a ; avoid negation using xor
%b_ = fadd double 0.0, %b ; avoid negation using xor
%c_ = fadd double 0.0, %c ; avoid negation using xor
@@ -795,6 +1598,78 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fnmsub_d_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a5
+; RV32I-NEXT: mv s3, a4
+; RV32I-NEXT: mv s4, a3
+; RV32I-NEXT: mv s5, a2
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv a0, s5
+; RV32I-NEXT: mv a1, s4
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a3, a1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call __muldf3 at plt
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a3, a1
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: call __subdf3 at plt
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmsub_d_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __muldf3 at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: call __subdf3 at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%a_ = fadd double 0.0, %a ; avoid negation using xor
%b_ = fadd double 0.0, %b ; avoid negation using xor
%1 = fmul contract double %a_, %b_
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index cc54a7aec786..98a7f36aa21d 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
define float @fcvt_s_d(double %a) nounwind {
; RV32IFD-LABEL: fcvt_s_d:
@@ -22,6 +26,24 @@ define float @fcvt_s_d(double %a) nounwind {
; RV64IFD-NEXT: fcvt.s.d ft0, ft0
; RV64IFD-NEXT: fmv.x.w a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __truncdfsf2 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __truncdfsf2 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptrunc double %a to float
ret float %1
}
@@ -44,6 +66,24 @@ define double @fcvt_d_s(float %a) nounwind {
; RV64IFD-NEXT: fcvt.d.s ft0, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __extendsfdf2 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __extendsfdf2 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fpext float %a to double
ret double %1
}
@@ -66,6 +106,24 @@ define i32 @fcvt_w_d(double %a) nounwind {
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fcvt.w.d a0, ft0, rtz
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_w_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __fixdfsi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_w_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __fixdfsi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptosi double %a to i32
ret i32 %1
}
@@ -99,6 +157,113 @@ define i32 @fcvt_w_d_sat(double %a) nounwind {
; RV64IFD-NEXT: .LBB3_2:
; RV64IFD-NEXT: fcvt.w.d a0, ft0, rtz
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_w_d_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: lui a3, 794112
+; RV32I-NEXT: mv s0, zero
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: call __gedf2 at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: call __fixdfsi at plt
+; RV32I-NEXT: lui s5, 524288
+; RV32I-NEXT: lui s4, 524288
+; RV32I-NEXT: blt s3, s0, .LBB3_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: .LBB3_2: # %start
+; RV32I-NEXT: lui a0, 269824
+; RV32I-NEXT: addi a3, a0, -1
+; RV32I-NEXT: lui a2, 1047552
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: call __gtdf2 at plt
+; RV32I-NEXT: bge s0, a0, .LBB3_4
+; RV32I-NEXT: # %bb.3:
+; RV32I-NEXT: addi s4, s5, -1
+; RV32I-NEXT: .LBB3_4: # %start
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: mv a2, s1
+; RV32I-NEXT: mv a3, s2
+; RV32I-NEXT: call __unorddf2 at plt
+; RV32I-NEXT: bne a0, s0, .LBB3_6
+; RV32I-NEXT: # %bb.5: # %start
+; RV32I-NEXT: mv s0, s4
+; RV32I-NEXT: .LBB3_6: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_w_d_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: addi a0, zero, -497
+; RV64I-NEXT: slli a1, a0, 53
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gedf2 at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixdfdi at plt
+; RV64I-NEXT: mv s1, zero
+; RV64I-NEXT: lui s4, 524288
+; RV64I-NEXT: lui s3, 524288
+; RV64I-NEXT: bltz s2, .LBB3_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: .LBB3_2: # %start
+; RV64I-NEXT: addi a0, zero, 527
+; RV64I-NEXT: slli a0, a0, 31
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a0, 22
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtdf2 at plt
+; RV64I-NEXT: bge s1, a0, .LBB3_4
+; RV64I-NEXT: # %bb.3:
+; RV64I-NEXT: addiw s3, s4, -1
+; RV64I-NEXT: .LBB3_4: # %start
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unorddf2 at plt
+; RV64I-NEXT: bne a0, s1, .LBB3_6
+; RV64I-NEXT: # %bb.5: # %start
+; RV64I-NEXT: mv s1, s3
+; RV64I-NEXT: .LBB3_6: # %start
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
start:
%0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
ret i32 %0
@@ -123,6 +288,24 @@ define i32 @fcvt_wu_d(double %a) nounwind {
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fcvt.wu.d a0, ft0, rtz
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_wu_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __fixunsdfsi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_wu_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __fixunsdfsi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptoui double %a to i32
ret i32 %1
}
@@ -156,6 +339,40 @@ define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) {
; RV64IFD-NEXT: mv a0, a1
; RV64IFD-NEXT: .LBB5_2:
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_wu_d_multiple_use:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: call __fixunsdfsi at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: addi a0, zero, 1
+; RV32I-NEXT: beqz a1, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB5_2:
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_wu_d_multiple_use:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: call __fixunsdfsi at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: addi a0, zero, 1
+; RV64I-NEXT: beqz a1, .LBB5_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: .LBB5_2:
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%a = fptoui double %x to i32
%b = icmp eq i32 %a, 0
%c = select i1 %b, i32 1, i32 %a
@@ -191,6 +408,86 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind {
; RV64IFD-NEXT: .LBB6_2:
; RV64IFD-NEXT: fcvt.wu.d a0, ft0, rtz
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_wu_d_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lui a0, 270080
+; RV32I-NEXT: addi a3, a0, -1
+; RV32I-NEXT: lui a2, 1048064
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __gtdf2 at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __gedf2 at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call __fixunsdfsi at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: bltz s3, .LBB6_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: .LBB6_2: # %start
+; RV32I-NEXT: addi a0, zero, -1
+; RV32I-NEXT: bgtz s2, .LBB6_4
+; RV32I-NEXT: # %bb.3: # %start
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB6_4: # %start
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_wu_d_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __gedf2 at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixunsdfdi at plt
+; RV64I-NEXT: mv s1, zero
+; RV64I-NEXT: bltz s2, .LBB6_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: .LBB6_2: # %start
+; RV64I-NEXT: addi a0, zero, 1055
+; RV64I-NEXT: slli a0, a0, 31
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a0, 21
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtdf2 at plt
+; RV64I-NEXT: blez a0, .LBB6_4
+; RV64I-NEXT: # %bb.3:
+; RV64I-NEXT: addi a0, zero, -1
+; RV64I-NEXT: srli s1, a0, 32
+; RV64I-NEXT: .LBB6_4: # %start
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
start:
%0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
ret i32 %0
@@ -213,6 +510,25 @@ define double @fcvt_d_w(i32 %a) nounwind {
; RV64IFD-NEXT: fcvt.d.w ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_w:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatsidf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_w:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: call __floatsidf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i32 %a to double
ret double %1
}
@@ -235,6 +551,26 @@ define double @fcvt_d_w_load(i32* %p) nounwind {
; RV64IFD-NEXT: fcvt.d.w ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_w_load:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 0(a0)
+; RV32I-NEXT: call __floatsidf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_w_load:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: call __floatsidf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%a = load i32, i32* %p
%1 = sitofp i32 %a to double
ret double %1
@@ -256,6 +592,25 @@ define double @fcvt_d_wu(i32 %a) nounwind {
; RV64IFD-NEXT: fcvt.d.wu ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_wu:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatunsidf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_wu:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: call __floatunsidf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i32 %a to double
ret double %1
}
@@ -278,6 +633,26 @@ define double @fcvt_d_wu_load(i32* %p) nounwind {
; RV64IFD-NEXT: fcvt.d.wu ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_wu_load:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 0(a0)
+; RV32I-NEXT: call __floatunsidf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_wu_load:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: call __floatunsidf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%a = load i32, i32* %p
%1 = uitofp i32 %a to double
ret double %1
@@ -298,6 +673,24 @@ define i64 @fcvt_l_d(double %a) nounwind {
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_l_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __fixdfdi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_l_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __fixdfdi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptosi double %a to i64
ret i64 %1
}
@@ -369,6 +762,153 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV64IFD-NEXT: .LBB12_2:
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_l_d_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -48
+; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: lui a0, 278016
+; RV32I-NEXT: addi s3, a0, -1
+; RV32I-NEXT: addi a2, zero, -1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a3, s3
+; RV32I-NEXT: call __gtdf2 at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: lui a3, 802304
+; RV32I-NEXT: mv s0, zero
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: call __gedf2 at plt
+; RV32I-NEXT: mv s6, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: call __fixdfdi at plt
+; RV32I-NEXT: mv s5, a1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: blt s6, s0, .LBB12_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: .LBB12_2: # %start
+; RV32I-NEXT: addi s6, zero, -1
+; RV32I-NEXT: blt s0, s4, .LBB12_4
+; RV32I-NEXT: # %bb.3: # %start
+; RV32I-NEXT: mv s6, a1
+; RV32I-NEXT: .LBB12_4: # %start
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: mv a2, s1
+; RV32I-NEXT: mv a3, s2
+; RV32I-NEXT: call __unorddf2 at plt
+; RV32I-NEXT: mv s4, s0
+; RV32I-NEXT: bne a0, s0, .LBB12_6
+; RV32I-NEXT: # %bb.5: # %start
+; RV32I-NEXT: mv s4, s6
+; RV32I-NEXT: .LBB12_6: # %start
+; RV32I-NEXT: lui a3, 802304
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: call __gedf2 at plt
+; RV32I-NEXT: lui s7, 524288
+; RV32I-NEXT: lui s6, 524288
+; RV32I-NEXT: blt a0, s0, .LBB12_8
+; RV32I-NEXT: # %bb.7: # %start
+; RV32I-NEXT: mv s6, s5
+; RV32I-NEXT: .LBB12_8: # %start
+; RV32I-NEXT: addi a2, zero, -1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: mv a3, s3
+; RV32I-NEXT: call __gtdf2 at plt
+; RV32I-NEXT: bge s0, a0, .LBB12_10
+; RV32I-NEXT: # %bb.9:
+; RV32I-NEXT: addi s6, s7, -1
+; RV32I-NEXT: .LBB12_10: # %start
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: mv a2, s1
+; RV32I-NEXT: mv a3, s2
+; RV32I-NEXT: call __unorddf2 at plt
+; RV32I-NEXT: bne a0, s0, .LBB12_12
+; RV32I-NEXT: # %bb.11: # %start
+; RV32I-NEXT: mv s0, s6
+; RV32I-NEXT: .LBB12_12: # %start
+; RV32I-NEXT: mv a0, s4
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_l_d_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: addi a0, zero, -481
+; RV64I-NEXT: slli a1, a0, 53
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gedf2 at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixdfdi at plt
+; RV64I-NEXT: mv s1, zero
+; RV64I-NEXT: addi s4, zero, -1
+; RV64I-NEXT: bltz s3, .LBB12_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: j .LBB12_3
+; RV64I-NEXT: .LBB12_2:
+; RV64I-NEXT: slli s2, s4, 63
+; RV64I-NEXT: .LBB12_3: # %start
+; RV64I-NEXT: addi a0, zero, 543
+; RV64I-NEXT: slli a0, a0, 53
+; RV64I-NEXT: addi a1, a0, -1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtdf2 at plt
+; RV64I-NEXT: bge s1, a0, .LBB12_5
+; RV64I-NEXT: # %bb.4:
+; RV64I-NEXT: srli s2, s4, 1
+; RV64I-NEXT: .LBB12_5: # %start
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unorddf2 at plt
+; RV64I-NEXT: bne a0, s1, .LBB12_7
+; RV64I-NEXT: # %bb.6: # %start
+; RV64I-NEXT: mv s1, s2
+; RV64I-NEXT: .LBB12_7: # %start
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
start:
%0 = tail call i64 @llvm.fptosi.sat.i64.f64(double %a)
ret i64 %0
@@ -390,6 +930,24 @@ define i64 @fcvt_lu_d(double %a) nounwind {
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_lu_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __fixunsdfdi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_lu_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __fixunsdfdi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptoui double %a to i64
ret i64 %1
}
@@ -448,6 +1006,116 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV64IFD-NEXT: .LBB14_2:
; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_lu_d_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lui a0, 278272
+; RV32I-NEXT: addi s3, a0, -1
+; RV32I-NEXT: addi a2, zero, -1
+; RV32I-NEXT: addi s2, zero, -1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a3, s3
+; RV32I-NEXT: call __gtdf2 at plt
+; RV32I-NEXT: mv s6, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __gedf2 at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call __fixunsdfdi at plt
+; RV32I-NEXT: mv s5, a1
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: bltz s4, .LBB14_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: .LBB14_2: # %start
+; RV32I-NEXT: addi s4, zero, -1
+; RV32I-NEXT: bgtz s6, .LBB14_4
+; RV32I-NEXT: # %bb.3: # %start
+; RV32I-NEXT: mv s4, a1
+; RV32I-NEXT: .LBB14_4: # %start
+; RV32I-NEXT: addi a2, zero, -1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: mv a3, s3
+; RV32I-NEXT: call __gtdf2 at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: mv a2, zero
+; RV32I-NEXT: mv a3, zero
+; RV32I-NEXT: call __gedf2 at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: bltz a0, .LBB14_6
+; RV32I-NEXT: # %bb.5: # %start
+; RV32I-NEXT: mv a1, s5
+; RV32I-NEXT: .LBB14_6: # %start
+; RV32I-NEXT: bgtz s3, .LBB14_8
+; RV32I-NEXT: # %bb.7: # %start
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: .LBB14_8: # %start
+; RV32I-NEXT: mv a0, s4
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_lu_d_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __gedf2 at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixunsdfdi at plt
+; RV64I-NEXT: mv s2, zero
+; RV64I-NEXT: bltz s1, .LBB14_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: .LBB14_2: # %start
+; RV64I-NEXT: addi a0, zero, 1087
+; RV64I-NEXT: slli a0, a0, 52
+; RV64I-NEXT: addi a1, a0, -1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtdf2 at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: addi a0, zero, -1
+; RV64I-NEXT: bgtz a1, .LBB14_4
+; RV64I-NEXT: # %bb.3: # %start
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: .LBB14_4: # %start
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
start:
%0 = tail call i64 @llvm.fptoui.sat.i64.f64(double %a)
ret i64 %0
@@ -478,6 +1146,24 @@ define i64 @fmv_x_d(double %a, double %b) nounwind {
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fmv_x_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmv_x_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fadd double %a, %b
%2 = bitcast double %1 to i64
ret i64 %2
@@ -498,6 +1184,24 @@ define double @fcvt_d_l(i64 %a) nounwind {
; RV64IFD-NEXT: fcvt.d.l ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_l:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatdidf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_l:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatdidf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i64 %a to double
ret double %1
}
@@ -517,6 +1221,24 @@ define double @fcvt_d_lu(i64 %a) nounwind {
; RV64IFD-NEXT: fcvt.d.lu ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_lu:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatundidf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_lu:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatundidf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i64 %a to double
ret double %1
}
@@ -546,6 +1268,24 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind {
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fmv_d_x:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmv_d_x:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = bitcast i64 %a to double
%2 = bitcast i64 %b to double
%3 = fadd double %1, %2
@@ -568,6 +1308,24 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind {
; RV64IFD-NEXT: fcvt.d.w ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_w_i8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatsidf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_w_i8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatsidf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i8 %a to double
ret double %1
}
@@ -588,6 +1346,24 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
; RV64IFD-NEXT: fcvt.d.wu ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_wu_i8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatunsidf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_wu_i8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatunsidf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i8 %a to double
ret double %1
}
@@ -608,6 +1384,24 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind {
; RV64IFD-NEXT: fcvt.d.w ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_w_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatsidf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_w_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatsidf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i16 %a to double
ret double %1
}
@@ -628,6 +1422,24 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
; RV64IFD-NEXT: fcvt.d.wu ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_wu_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatunsidf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_wu_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatunsidf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i16 %a to double
ret double %1
}
@@ -647,6 +1459,51 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) {
; RV64IFD-NEXT: fcvt.d.w ft0, a0
; RV64IFD-NEXT: fsd ft0, 0(a1)
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_w_demanded_bits:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: addi s1, a0, 1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __floatsidf at plt
+; RV32I-NEXT: sw a1, 4(s0)
+; RV32I-NEXT: sw a0, 0(s0)
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_w_demanded_bits:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
+; RV64I-NEXT: .cfi_offset s1, -24
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: addiw s1, a0, 1
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __floatsidf at plt
+; RV64I-NEXT: sd a0, 0(s0)
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%3 = add i32 %0, 1
%4 = sitofp i32 %3 to double
store double %4, double* %1, align 8
@@ -668,6 +1525,51 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) {
; RV64IFD-NEXT: fcvt.d.wu ft0, a0
; RV64IFD-NEXT: fsd ft0, 0(a1)
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_wu_demanded_bits:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: addi s1, a0, 1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __floatunsidf at plt
+; RV32I-NEXT: sw a1, 4(s0)
+; RV32I-NEXT: sw a0, 0(s0)
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_wu_demanded_bits:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
+; RV64I-NEXT: .cfi_offset s1, -24
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: addiw s1, a0, 1
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __floatunsidf at plt
+; RV64I-NEXT: sd a0, 0(s0)
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%3 = add i32 %0, 1
%4 = uitofp i32 %3 to double
store double %4, double* %1, align 8
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll
index 1caec05cf9a9..fe2bada8741a 100644
--- a/llvm/test/CodeGen/RISCV/double-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(double %a, double %b) nounwind {
; RV32IFD-LABEL: fcmp_false:
@@ -14,6 +18,16 @@ define i32 @fcmp_false(double %a, double %b) nounwind {
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: mv a0, zero
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_false:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a0, zero
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_false:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a0, zero
+; RV64I-NEXT: ret
%1 = fcmp false double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -39,6 +53,26 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_oeq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __eqdf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_oeq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __eqdf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp oeq double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -64,6 +98,26 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ogt:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __gtdf2 at plt
+; RV32I-NEXT: sgtz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ogt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __gtdf2 at plt
+; RV64I-NEXT: sgtz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ogt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -89,6 +143,28 @@ define i32 @fcmp_oge(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_oge:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __gedf2 at plt
+; RV32I-NEXT: addi a1, zero, -1
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_oge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __gedf2 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp oge double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -114,6 +190,26 @@ define i32 @fcmp_olt(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_olt:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __ltdf2 at plt
+; RV32I-NEXT: slti a0, a0, 0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_olt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __ltdf2 at plt
+; RV64I-NEXT: slti a0, a0, 0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp olt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -139,6 +235,26 @@ define i32 @fcmp_ole(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ole:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __ledf2 at plt
+; RV32I-NEXT: slti a0, a0, 1
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ole:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __ledf2 at plt
+; RV64I-NEXT: slti a0, a0, 1
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ole double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -168,6 +284,60 @@ define i32 @fcmp_one(double %a, double %b) nounwind {
; RV64IFD-NEXT: flt.d a1, ft0, ft1
; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_one:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a3
+; RV32I-NEXT: mv s3, a2
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: call __eqdf2 at plt
+; RV32I-NEXT: snez s4, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a3, s2
+; RV32I-NEXT: call __unorddf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: and a0, a0, s4
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_one:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: call __eqdf2 at plt
+; RV64I-NEXT: snez s2, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unorddf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: and a0, a0, s2
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fcmp one double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -197,6 +367,26 @@ define i32 @fcmp_ord(double %a, double %b) nounwind {
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ord:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __unorddf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ord:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __unorddf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ord double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -228,6 +418,60 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ueq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a3
+; RV32I-NEXT: mv s3, a2
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: call __eqdf2 at plt
+; RV32I-NEXT: seqz s4, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a3, s2
+; RV32I-NEXT: call __unorddf2 at plt
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: or a0, a0, s4
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ueq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: call __eqdf2 at plt
+; RV64I-NEXT: seqz s2, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unorddf2 at plt
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: or a0, a0, s2
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fcmp ueq double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -255,6 +499,26 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind {
; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ugt:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __ledf2 at plt
+; RV32I-NEXT: sgtz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ugt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __ledf2 at plt
+; RV64I-NEXT: sgtz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ugt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -282,6 +546,28 @@ define i32 @fcmp_uge(double %a, double %b) nounwind {
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_uge:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __ltdf2 at plt
+; RV32I-NEXT: addi a1, zero, -1
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_uge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __ltdf2 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp uge double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -309,6 +595,26 @@ define i32 @fcmp_ult(double %a, double %b) nounwind {
; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ult:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __gedf2 at plt
+; RV32I-NEXT: slti a0, a0, 0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ult:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __gedf2 at plt
+; RV64I-NEXT: slti a0, a0, 0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ult double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -336,6 +642,26 @@ define i32 @fcmp_ule(double %a, double %b) nounwind {
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ule:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __gtdf2 at plt
+; RV32I-NEXT: slti a0, a0, 1
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ule:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __gtdf2 at plt
+; RV64I-NEXT: slti a0, a0, 1
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ule double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -363,6 +689,26 @@ define i32 @fcmp_une(double %a, double %b) nounwind {
; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_une:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __nedf2 at plt
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_une:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __nedf2 at plt
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp une double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -394,6 +740,26 @@ define i32 @fcmp_uno(double %a, double %b) nounwind {
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_uno:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __unorddf2 at plt
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_uno:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __unorddf2 at plt
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp uno double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -409,6 +775,16 @@ define i32 @fcmp_true(double %a, double %b) nounwind {
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi a0, zero, 1
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fcmp_true:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a0, zero, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_true:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a0, zero, 1
+; RV64I-NEXT: ret
%1 = fcmp true double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
index c03b65f515f0..5a3b6e457a64 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
@@ -3,6 +3,10 @@
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32IFD %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IFD %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
+; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
+; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
declare double @llvm.sqrt.f64(double)
@@ -26,6 +30,24 @@ define double @sqrt_f64(double %a) nounwind {
; RV64IFD-NEXT: fsqrt.d ft0, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: sqrt_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call sqrt at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: sqrt_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call sqrt at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.sqrt.f64(double %a)
ret double %1
}
@@ -51,6 +73,25 @@ define double @powi_f64(double %a, i32 %b) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: powi_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __powidf2 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: powi_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sext.w a1, a1
+; RV64I-NEXT: call __powidf2 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.powi.f64.i32(double %a, i32 %b)
ret double %1
}
@@ -75,6 +116,24 @@ define double @sin_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: sin_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call sin at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: sin_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call sin at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.sin.f64(double %a)
ret double %1
}
@@ -99,6 +158,24 @@ define double @cos_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: cos_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call cos at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: cos_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call cos at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.cos.f64(double %a)
ret double %1
}
@@ -154,6 +231,55 @@ define double @sincos_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: sincos_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: call sin at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call cos at plt
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a3, a1
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: sincos_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: call sin at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call cos at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = call double @llvm.sin.f64(double %a)
%2 = call double @llvm.cos.f64(double %a)
%3 = fadd double %1, %2
@@ -180,6 +306,24 @@ define double @pow_f64(double %a, double %b) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: pow_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call pow at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: pow_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call pow at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.pow.f64(double %a, double %b)
ret double %1
}
@@ -204,6 +348,24 @@ define double @exp_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: exp_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call exp at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: exp_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call exp at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.exp.f64(double %a)
ret double %1
}
@@ -228,6 +390,24 @@ define double @exp2_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: exp2_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call exp2 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: exp2_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call exp2 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.exp2.f64(double %a)
ret double %1
}
@@ -252,6 +432,24 @@ define double @log_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: log_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call log at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: log_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call log at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.log.f64(double %a)
ret double %1
}
@@ -276,6 +474,24 @@ define double @log10_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: log10_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call log10 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: log10_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call log10 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.log10.f64(double %a)
ret double %1
}
@@ -300,6 +516,24 @@ define double @log2_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: log2_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call log2 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: log2_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call log2 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.log2.f64(double %a)
ret double %1
}
@@ -334,6 +568,24 @@ define double @fma_f64(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fma_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fma at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fma_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fma at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.fma.f64(double %a, double %b, double %c)
ret double %1
}
@@ -368,6 +620,38 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fmuladd_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a5
+; RV32I-NEXT: mv s1, a4
+; RV32I-NEXT: call __muldf3 at plt
+; RV32I-NEXT: mv a2, s1
+; RV32I-NEXT: mv a3, s0
+; RV32I-NEXT: call __adddf3 at plt
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmuladd_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: call __muldf3 at plt
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __adddf3 at plt
+; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
ret double %1
}
@@ -388,6 +672,20 @@ define double @fabs_f64(double %a) nounwind {
; RV64IFD-NEXT: srli a1, a1, 1
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: fabs_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fabs_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: srli a1, a1, 1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
%1 = call double @llvm.fabs.f64(double %a)
ret double %1
}
@@ -418,6 +716,24 @@ define double @minnum_f64(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmin.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: minnum_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fmin at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: minnum_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fmin at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.minnum.f64(double %a, double %b)
ret double %1
}
@@ -448,6 +764,24 @@ define double @maxnum_f64(double %a, double %b) nounwind {
; RV64IFD-NEXT: fmax.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: maxnum_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fmax at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: maxnum_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fmax at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.maxnum.f64(double %a, double %b)
ret double %1
}
@@ -495,6 +829,25 @@ define double @copysign_f64(double %a, double %b) nounwind {
; RV64IFD-NEXT: fsgnj.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: copysign_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: and a3, a3, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: copysign_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a2, zero, -1
+; RV64I-NEXT: slli a3, a2, 63
+; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: srli a2, a2, 1
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
%1 = call double @llvm.copysign.f64(double %a, double %b)
ret double %1
}
@@ -519,6 +872,24 @@ define double @floor_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: floor_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call floor at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: floor_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call floor at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.floor.f64(double %a)
ret double %1
}
@@ -543,6 +914,24 @@ define double @ceil_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: ceil_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call ceil at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ceil_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call ceil at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.ceil.f64(double %a)
ret double %1
}
@@ -567,6 +956,24 @@ define double @trunc_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: trunc_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call trunc at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: trunc_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call trunc at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.trunc.f64(double %a)
ret double %1
}
@@ -591,6 +998,24 @@ define double @rint_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: rint_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call rint at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: rint_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call rint at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.rint.f64(double %a)
ret double %1
}
@@ -615,6 +1040,24 @@ define double @nearbyint_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: nearbyint_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call nearbyint at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: nearbyint_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call nearbyint at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.nearbyint.f64(double %a)
ret double %1
}
@@ -639,6 +1082,24 @@ define double @round_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: round_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call round at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: round_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call round at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.round.f64(double %a)
ret double %1
}
@@ -663,6 +1124,24 @@ define double @roundeven_f64(double %a) nounwind {
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: roundeven_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call roundeven at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: roundeven_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call roundeven at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call double @llvm.roundeven.f64(double %a)
ret double %1
}
@@ -681,6 +1160,24 @@ define iXLen @lrint_f64(float %a) nounwind {
; RV64IFD-NEXT: fmv.w.x ft0, a0
; RV64IFD-NEXT: fcvt.l.s a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: lrint_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call lrintf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: lrint_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call lrintf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call iXLen @llvm.lrint.iXLen.f64(float %a)
ret iXLen %1
}
@@ -699,6 +1196,24 @@ define iXLen @lround_f64(float %a) nounwind {
; RV64IFD-NEXT: fmv.w.x ft0, a0
; RV64IFD-NEXT: fcvt.l.s a0, ft0, rmm
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: lround_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call lroundf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: lround_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call lroundf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call iXLen @llvm.lround.iXLen.f64(float %a)
ret iXLen %1
}
@@ -720,6 +1235,24 @@ define i64 @llrint_f64(float %a) nounwind {
; RV64IFD-NEXT: fmv.w.x ft0, a0
; RV64IFD-NEXT: fcvt.l.s a0, ft0
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: llrint_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call llrintf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: llrint_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call llrintf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call i64 @llvm.llrint.i64.f64(float %a)
ret i64 %1
}
@@ -741,6 +1274,24 @@ define i64 @llround_f64(float %a) nounwind {
; RV64IFD-NEXT: fmv.w.x ft0, a0
; RV64IFD-NEXT: fcvt.l.s a0, ft0, rmm
; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: llround_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call llroundf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: llround_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call llroundf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call i64 @llvm.llround.i64.f64(float %a)
ret i64 %1
}
diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll
index d302dd5ebc0a..483ab80731c4 100644
--- a/llvm/test/CodeGen/RISCV/float-arith.ll
+++ b/llvm/test/CodeGen/RISCV/float-arith.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
; These tests are each targeted at a particular RISC-V FPU instruction. Most
; other files in this folder exercise LLVM IR instructions that don't directly
@@ -24,6 +28,24 @@ define float @fadd_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fadd_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fadd_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fadd float %a, %b
ret float %1
}
@@ -44,6 +66,24 @@ define float @fsub_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fsub.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fsub_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __subsf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsub_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __subsf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fsub float %a, %b
ret float %1
}
@@ -64,6 +104,24 @@ define float @fmul_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fmul.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fmul_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmul_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fmul float %a, %b
ret float %1
}
@@ -84,6 +142,24 @@ define float @fdiv_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fdiv.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fdiv_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __divsf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fdiv_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __divsf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fdiv float %a, %b
ret float %1
}
@@ -104,6 +180,24 @@ define float @fsqrt_s(float %a) nounwind {
; RV64IF-NEXT: fsqrt.s ft0, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fsqrt_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call sqrtf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsqrt_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call sqrtf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.sqrt.f32(float %a)
ret float %1
}
@@ -126,6 +220,24 @@ define float @fsgnj_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fsgnj.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fsgnj_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsgnj_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a2, 524288
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: addiw a2, a2, -1
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
%1 = call float @llvm.copysign.f32(float %a, float %b)
ret float %1
}
@@ -148,6 +260,34 @@ define i32 @fneg_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fneg.s ft1, ft0
; RV64IF-NEXT: feq.s a0, ft0, ft1
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fneg_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a1, a0, a1
+; RV32I-NEXT: call __eqsf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fneg_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a1, a0, a1
+; RV64I-NEXT: call __eqsf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fadd float %a, %a
%2 = fneg float %1
%3 = fcmp oeq float %1, %2
@@ -175,6 +315,42 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fsgnjn.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fsgnjn_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: addi a2, a1, -1
+; RV32I-NEXT: and a2, s0, a2
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: or a0, a2, a0
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsgnjn_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: addiw a2, a1, -1
+; RV64I-NEXT: and a2, s0, a2
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: or a0, a2, a0
+; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fadd float %a, %b
%2 = fneg float %1
%3 = call float @llvm.copysign.f32(float %a, float %2)
@@ -205,6 +381,34 @@ define float @fabs_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fabs_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: lui a0, 524288
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fabs_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: lui a0, 524288
+; RV64I-NEXT: addiw a0, a0, -1
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fadd float %a, %b
%2 = call float @llvm.fabs.f32(float %1)
%3 = fadd float %2, %1
@@ -229,6 +433,24 @@ define float @fmin_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fmin.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fmin_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fminf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmin_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fminf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.minnum.f32(float %a, float %b)
ret float %1
}
@@ -251,6 +473,24 @@ define float @fmax_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fmax.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fmax_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fmaxf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmax_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fmaxf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.maxnum.f32(float %a, float %b)
ret float %1
}
@@ -269,6 +509,26 @@ define i32 @feq_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: feq_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __eqsf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: feq_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __eqsf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp oeq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -288,6 +548,26 @@ define i32 @flt_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: flt_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __ltsf2 at plt
+; RV32I-NEXT: slti a0, a0, 0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: flt_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __ltsf2 at plt
+; RV64I-NEXT: slti a0, a0, 0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp olt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -307,6 +587,26 @@ define i32 @fle_s(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fle_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __lesf2 at plt
+; RV32I-NEXT: slti a0, a0, 1
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fle_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __lesf2 at plt
+; RV64I-NEXT: slti a0, a0, 1
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -332,6 +632,24 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fmadd_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmadd_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.fma.f32(float %a, float %b, float %c)
ret float %1
}
@@ -358,6 +676,50 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmsub.s ft0, ft1, ft0, ft2
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fmsub_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmsub_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a2, a0, a1
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%c_ = fadd float 0.0, %c ; avoid negation using xor
%negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
@@ -388,6 +750,62 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fnmadd.s ft0, ft2, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fnmadd_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: xor a1, s1, a2
+; RV32I-NEXT: xor a2, a0, a2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmadd_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: lui a2, 524288
+; RV64I-NEXT: xor a1, s1, a2
+; RV64I-NEXT: xor a2, a0, a2
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: mv a1, s2
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a
%c_ = fadd float 0.0, %c
%nega = fsub float -0.0, %a_
@@ -420,6 +838,62 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fnmadd.s ft0, ft2, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fnmadd_s_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: xor a1, s1, a2
+; RV32I-NEXT: xor a2, a0, a2
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmadd_s_2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: lui a2, 524288
+; RV64I-NEXT: xor a1, s1, a2
+; RV64I-NEXT: xor a2, a0, a2
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%b_ = fadd float 0.0, %b
%c_ = fadd float 0.0, %c
%negb = fsub float -0.0, %b_
@@ -450,6 +924,48 @@ define float @fnmsub_s(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fnmsub_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmsub_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: mv a1, s1
+; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a
%nega = fsub float -0.0, %a_
%1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
@@ -478,6 +994,50 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fnmsub_s_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a1, a0, a1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmsub_s_2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a1, a0, a1
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%b_ = fadd float 0.0, %b
%negb = fsub float -0.0, %b_
%1 = call float @llvm.fma.f32(float %a, float %negb, float %c)
@@ -502,6 +1062,34 @@ define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fmadd_s_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmadd_s_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fmul contract float %a, %b
%2 = fadd contract float %1, %c
ret float %2
@@ -529,6 +1117,56 @@ define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmsub.s ft0, ft1, ft0, ft2
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fmsub_s_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __subsf3 at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmsub_s_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, s2
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __subsf3 at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%c_ = fadd float 0.0, %c ; avoid negation using xor
%1 = fmul contract float %a, %b
%2 = fsub contract float %1, %c_
@@ -561,6 +1199,78 @@ define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fnmadd.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fnmadd_s_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a2
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __subsf3 at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmadd_s_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a0, s3
+; RV64I-NEXT: mv a1, s1
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __subsf3 at plt
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a ; avoid negation using xor
%b_ = fadd float 0.0, %b ; avoid negation using xor
%c_ = fadd float 0.0, %c ; avoid negation using xor
@@ -594,6 +1304,62 @@ define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fnmsub_s_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a2
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: call __subsf3 at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmsub_s_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: call __subsf3 at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a ; avoid negation using xor
%b_ = fadd float 0.0, %b ; avoid negation using xor
%1 = fmul contract float %a_, %b_
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index f1fca49df5fb..ac83a5cbd5d3 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
; For RV64F, fcvt.l.s is semantically equivalent to fcvt.w.s in this case
; because fptosi will produce poison if the result doesn't fit into an i32.
@@ -18,6 +22,24 @@ define i32 @fcvt_w_s(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_w_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __fixsfsi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_w_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __fixsfsi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptosi float %a to i32
ret i32 %1
}
@@ -46,14 +68,106 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV64IF-NEXT: .LBB1_2:
; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_w_s_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lui a1, 847872
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __fixsfsi at plt
+; RV32I-NEXT: mv s1, zero
+; RV32I-NEXT: lui s4, 524288
+; RV32I-NEXT: lui s3, 524288
+; RV32I-NEXT: bltz s2, .LBB1_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: .LBB1_2: # %start
+; RV32I-NEXT: lui a0, 323584
+; RV32I-NEXT: addi a1, a0, -1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: bge s1, a0, .LBB1_4
+; RV32I-NEXT: # %bb.3:
+; RV32I-NEXT: addi s3, s4, -1
+; RV32I-NEXT: .LBB1_4: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: bne a0, s1, .LBB1_6
+; RV32I-NEXT: # %bb.5: # %start
+; RV32I-NEXT: mv s1, s3
+; RV32I-NEXT: .LBB1_6: # %start
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_w_s_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lui a1, 847872
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixsfdi at plt
+; RV64I-NEXT: mv s1, zero
+; RV64I-NEXT: lui s4, 524288
+; RV64I-NEXT: lui s3, 524288
+; RV64I-NEXT: bltz s2, .LBB1_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: .LBB1_2: # %start
+; RV64I-NEXT: lui a0, 323584
+; RV64I-NEXT: addiw a1, a0, -1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: bge s1, a0, .LBB1_4
+; RV64I-NEXT: # %bb.3:
+; RV64I-NEXT: addiw s3, s4, -1
+; RV64I-NEXT: .LBB1_4: # %start
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unordsf2 at plt
+; RV64I-NEXT: bne a0, s1, .LBB1_6
+; RV64I-NEXT: # %bb.5: # %start
+; RV64I-NEXT: mv s1, s3
+; RV64I-NEXT: .LBB1_6: # %start
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
start:
%0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %0
}
declare i32 @llvm.fptosi.sat.i32.f32(float)
-; For RV64F, fcvt.lu.s is semantically equivalent to fcvt.wu.s in this case
-; because fptoui will produce poison if the result doesn't fit into an i32.
define i32 @fcvt_wu_s(float %a) nounwind {
; RV32IF-LABEL: fcvt_wu_s:
; RV32IF: # %bb.0:
@@ -66,6 +180,24 @@ define i32 @fcvt_wu_s(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_wu_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __fixunssfsi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_wu_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __fixunssfsi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptoui float %a to i32
ret i32 %1
}
@@ -94,6 +226,40 @@ define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) {
; RV64IF-NEXT: mv a0, a1
; RV64IF-NEXT: .LBB3_2:
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_wu_s_multiple_use:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: call __fixunssfsi at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: addi a0, zero, 1
+; RV32I-NEXT: beqz a1, .LBB3_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB3_2:
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_wu_s_multiple_use:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: call __fixunssfsi at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: addi a0, zero, 1
+; RV64I-NEXT: beqz a1, .LBB3_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: .LBB3_2:
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%a = fptoui float %x to i32
%b = icmp eq i32 %a, 0
%c = select i1 %b, i32 1, i32 %a
@@ -124,6 +290,76 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV64IF-NEXT: .LBB4_2:
; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_wu_s_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __fixunssfsi at plt
+; RV32I-NEXT: mv s2, zero
+; RV32I-NEXT: bltz s1, .LBB4_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: .LBB4_2: # %start
+; RV32I-NEXT: lui a0, 325632
+; RV32I-NEXT: addi a1, a0, -1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: addi a0, zero, -1
+; RV32I-NEXT: bgtz a1, .LBB4_4
+; RV32I-NEXT: # %bb.3: # %start
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: .LBB4_4: # %start
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_wu_s_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixunssfdi at plt
+; RV64I-NEXT: mv s1, zero
+; RV64I-NEXT: bltz s2, .LBB4_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: .LBB4_2: # %start
+; RV64I-NEXT: lui a0, 325632
+; RV64I-NEXT: addiw a1, a0, -1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: blez a0, .LBB4_4
+; RV64I-NEXT: # %bb.3:
+; RV64I-NEXT: addi a0, zero, -1
+; RV64I-NEXT: srli s1, a0, 32
+; RV64I-NEXT: .LBB4_4: # %start
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
start:
%0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %0
@@ -146,6 +382,24 @@ define i32 @fmv_x_w(float %a, float %b) nounwind {
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fmv_x_w:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmv_x_w:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
; Ensure fmv.x.w is generated even for a soft float calling convention
%1 = fadd float %a, %b
%2 = bitcast float %1 to i32
@@ -164,6 +418,25 @@ define float @fcvt_s_w(i32 %a) nounwind {
; RV64IF-NEXT: fcvt.s.w ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_w:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatsisf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_w:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: call __floatsisf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i32 %a to float
ret float %1
}
@@ -182,6 +455,26 @@ define float @fcvt_s_w_load(i32* %p) nounwind {
; RV64IF-NEXT: fcvt.s.w ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_w_load:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 0(a0)
+; RV32I-NEXT: call __floatsisf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_w_load:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: call __floatsisf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%a = load i32, i32* %p
%1 = sitofp i32 %a to float
ret float %1
@@ -199,6 +492,25 @@ define float @fcvt_s_wu(i32 %a) nounwind {
; RV64IF-NEXT: fcvt.s.wu ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_wu:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatunsisf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_wu:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: call __floatunsisf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i32 %a to float
ret float %1
}
@@ -217,6 +529,26 @@ define float @fcvt_s_wu_load(i32* %p) nounwind {
; RV64IF-NEXT: fcvt.s.wu ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_wu_load:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 0(a0)
+; RV32I-NEXT: call __floatunsisf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_wu_load:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: call __floatunsisf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%a = load i32, i32* %p
%1 = uitofp i32 %a to float
ret float %1
@@ -238,6 +570,24 @@ define float @fmv_w_x(i32 %a, i32 %b) nounwind {
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fmv_w_x:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmv_w_x:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
; Ensure fmv.w.x is generated even for a soft float calling convention
%1 = bitcast i32 %a to float
%2 = bitcast i32 %b to float
@@ -260,6 +610,24 @@ define i64 @fcvt_l_s(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_l_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __fixsfdi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_l_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __fixsfdi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptosi float %a to i64
ret i64 %1
}
@@ -332,6 +700,133 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV64IF-NEXT: .LBB12_2:
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_l_s_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lui a1, 913408
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __fixsfdi at plt
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: mv s1, zero
+; RV32I-NEXT: mv s5, zero
+; RV32I-NEXT: bltz s3, .LBB12_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s5, a0
+; RV32I-NEXT: .LBB12_2: # %start
+; RV32I-NEXT: lui a0, 389120
+; RV32I-NEXT: addi s4, a0, -1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s4
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: addi s6, zero, -1
+; RV32I-NEXT: blt s1, a0, .LBB12_4
+; RV32I-NEXT: # %bb.3: # %start
+; RV32I-NEXT: mv s6, s5
+; RV32I-NEXT: .LBB12_4: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: mv s3, s1
+; RV32I-NEXT: bne a0, s1, .LBB12_6
+; RV32I-NEXT: # %bb.5: # %start
+; RV32I-NEXT: mv s3, s6
+; RV32I-NEXT: .LBB12_6: # %start
+; RV32I-NEXT: lui a1, 913408
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: lui s6, 524288
+; RV32I-NEXT: lui s5, 524288
+; RV32I-NEXT: blt a0, s1, .LBB12_8
+; RV32I-NEXT: # %bb.7: # %start
+; RV32I-NEXT: mv s5, s2
+; RV32I-NEXT: .LBB12_8: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s4
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: bge s1, a0, .LBB12_10
+; RV32I-NEXT: # %bb.9:
+; RV32I-NEXT: addi s5, s6, -1
+; RV32I-NEXT: .LBB12_10: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: bne a0, s1, .LBB12_12
+; RV32I-NEXT: # %bb.11: # %start
+; RV32I-NEXT: mv s1, s5
+; RV32I-NEXT: .LBB12_12: # %start
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_l_s_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lui a1, 913408
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixsfdi at plt
+; RV64I-NEXT: mv s1, zero
+; RV64I-NEXT: addi s4, zero, -1
+; RV64I-NEXT: bltz s3, .LBB12_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: j .LBB12_3
+; RV64I-NEXT: .LBB12_2:
+; RV64I-NEXT: slli s2, s4, 63
+; RV64I-NEXT: .LBB12_3: # %start
+; RV64I-NEXT: lui a0, 389120
+; RV64I-NEXT: addiw a1, a0, -1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: bge s1, a0, .LBB12_5
+; RV64I-NEXT: # %bb.4:
+; RV64I-NEXT: srli s2, s4, 1
+; RV64I-NEXT: .LBB12_5: # %start
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unordsf2 at plt
+; RV64I-NEXT: bne a0, s1, .LBB12_7
+; RV64I-NEXT: # %bb.6: # %start
+; RV64I-NEXT: mv s1, s2
+; RV64I-NEXT: .LBB12_7: # %start
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
start:
%0 = tail call i64 @llvm.fptosi.sat.i64.f32(float %a)
ret i64 %0
@@ -353,6 +848,24 @@ define i64 @fcvt_lu_s(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_lu_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __fixunssfdi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_lu_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __fixunssfdi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptoui float %a to i64
ret i64 %1
}
@@ -411,6 +924,101 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV64IF-NEXT: .LBB14_2:
; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_lu_s_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __fixunssfdi at plt
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: mv s5, zero
+; RV32I-NEXT: bltz s1, .LBB14_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s5, a0
+; RV32I-NEXT: .LBB14_2: # %start
+; RV32I-NEXT: lui a0, 391168
+; RV32I-NEXT: addi s1, a0, -1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: addi s3, zero, -1
+; RV32I-NEXT: addi s4, zero, -1
+; RV32I-NEXT: bgtz a0, .LBB14_4
+; RV32I-NEXT: # %bb.3: # %start
+; RV32I-NEXT: mv s4, s5
+; RV32I-NEXT: .LBB14_4: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s5, zero
+; RV32I-NEXT: bltz a0, .LBB14_6
+; RV32I-NEXT: # %bb.5: # %start
+; RV32I-NEXT: mv s5, s2
+; RV32I-NEXT: .LBB14_6: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: bgtz a0, .LBB14_8
+; RV32I-NEXT: # %bb.7: # %start
+; RV32I-NEXT: mv s3, s5
+; RV32I-NEXT: .LBB14_8: # %start
+; RV32I-NEXT: mv a0, s4
+; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_lu_s_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixunssfdi at plt
+; RV64I-NEXT: mv s2, zero
+; RV64I-NEXT: bltz s1, .LBB14_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: .LBB14_2: # %start
+; RV64I-NEXT: lui a0, 391168
+; RV64I-NEXT: addiw a1, a0, -1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: addi a0, zero, -1
+; RV64I-NEXT: bgtz a1, .LBB14_4
+; RV64I-NEXT: # %bb.3: # %start
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: .LBB14_4: # %start
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
start:
%0 = tail call i64 @llvm.fptoui.sat.i64.f32(float %a)
ret i64 %0
@@ -432,6 +1040,24 @@ define float @fcvt_s_l(i64 %a) nounwind {
; RV64IF-NEXT: fcvt.s.l ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_l:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatdisf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_l:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatdisf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i64 %a to float
ret float %1
}
@@ -451,6 +1077,24 @@ define float @fcvt_s_lu(i64 %a) nounwind {
; RV64IF-NEXT: fcvt.s.lu ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_lu:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatundisf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_lu:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatundisf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i64 %a to float
ret float %1
}
@@ -467,6 +1111,24 @@ define float @fcvt_s_w_i8(i8 signext %a) nounwind {
; RV64IF-NEXT: fcvt.s.w ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_w_i8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatsisf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_w_i8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatsisf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i8 %a to float
ret float %1
}
@@ -483,6 +1145,24 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
; RV64IF-NEXT: fcvt.s.wu ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_wu_i8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatunsisf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_wu_i8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatunsisf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i8 %a to float
ret float %1
}
@@ -499,6 +1179,24 @@ define float @fcvt_s_w_i16(i16 signext %a) nounwind {
; RV64IF-NEXT: fcvt.s.w ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_w_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatsisf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_w_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatsisf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i16 %a to float
ret float %1
}
@@ -515,6 +1213,24 @@ define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
; RV64IF-NEXT: fcvt.s.wu ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_wu_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatunsisf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_wu_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatunsisf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i16 %a to float
ret float %1
}
@@ -534,6 +1250,50 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
; RV64IF-NEXT: fcvt.s.w ft0, a0
; RV64IF-NEXT: fsw ft0, 0(a1)
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_w_demanded_bits:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: addi s1, a0, 1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __floatsisf at plt
+; RV32I-NEXT: sw a0, 0(s0)
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_w_demanded_bits:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
+; RV64I-NEXT: .cfi_offset s1, -24
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: addiw s1, a0, 1
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __floatsisf at plt
+; RV64I-NEXT: sw a0, 0(s0)
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%3 = add i32 %0, 1
%4 = sitofp i32 %3 to float
store float %4, float* %1, align 4
@@ -555,6 +1315,50 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) {
; RV64IF-NEXT: fcvt.s.wu ft0, a0
; RV64IF-NEXT: fsw ft0, 0(a1)
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_wu_demanded_bits:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: addi s1, a0, 1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __floatunsisf at plt
+; RV32I-NEXT: sw a0, 0(s0)
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_wu_demanded_bits:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
+; RV64I-NEXT: .cfi_offset s1, -24
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: addiw s1, a0, 1
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __floatunsisf at plt
+; RV64I-NEXT: sw a0, 0(s0)
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%3 = add i32 %0, 1
%4 = uitofp i32 %3 to float
store float %4, float* %1, align 4
diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll
index c19013fce4b0..272aee752317 100644
--- a/llvm/test/CodeGen/RISCV/float-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_false:
@@ -14,6 +18,16 @@ define i32 @fcmp_false(float %a, float %b) nounwind {
; RV64IF: # %bb.0:
; RV64IF-NEXT: mv a0, zero
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_false:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a0, zero
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_false:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a0, zero
+; RV64I-NEXT: ret
%1 = fcmp false float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -33,6 +47,26 @@ define i32 @fcmp_oeq(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_oeq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __eqsf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_oeq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __eqsf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp oeq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -52,6 +86,26 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ogt:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: sgtz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ogt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: sgtz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ogt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -71,6 +125,28 @@ define i32 @fcmp_oge(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_oge:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: addi a1, zero, -1
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_oge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp oge float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -90,6 +166,26 @@ define i32 @fcmp_olt(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_olt:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __ltsf2 at plt
+; RV32I-NEXT: slti a0, a0, 0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_olt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __ltsf2 at plt
+; RV64I-NEXT: slti a0, a0, 0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp olt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -109,6 +205,26 @@ define i32 @fcmp_ole(float %a, float %b) nounwind {
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ole:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __lesf2 at plt
+; RV32I-NEXT: slti a0, a0, 1
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ole:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __lesf2 at plt
+; RV64I-NEXT: slti a0, a0, 1
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -132,6 +248,52 @@ define i32 @fcmp_one(float %a, float %b) nounwind {
; RV64IF-NEXT: flt.s a1, ft0, ft1
; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_one:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: call __eqsf2 at plt
+; RV32I-NEXT: snez s2, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: and a0, a0, s2
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_one:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: call __eqsf2 at plt
+; RV64I-NEXT: snez s2, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unordsf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: and a0, a0, s2
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fcmp one float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -155,6 +317,26 @@ define i32 @fcmp_ord(float %a, float %b) nounwind {
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ord:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ord:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __unordsf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ord float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -180,6 +362,52 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind {
; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ueq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: call __eqsf2 at plt
+; RV32I-NEXT: seqz s2, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: or a0, a0, s2
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ueq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: call __eqsf2 at plt
+; RV64I-NEXT: seqz s2, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unordsf2 at plt
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: or a0, a0, s2
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fcmp ueq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -201,6 +429,26 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind {
; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ugt:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __lesf2 at plt
+; RV32I-NEXT: sgtz a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ugt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __lesf2 at plt
+; RV64I-NEXT: sgtz a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ugt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -222,6 +470,28 @@ define i32 @fcmp_uge(float %a, float %b) nounwind {
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_uge:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __ltsf2 at plt
+; RV32I-NEXT: addi a1, zero, -1
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_uge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __ltsf2 at plt
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp uge float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -243,6 +513,26 @@ define i32 @fcmp_ult(float %a, float %b) nounwind {
; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ult:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: slti a0, a0, 0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ult:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: slti a0, a0, 0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ult float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -264,6 +554,26 @@ define i32 @fcmp_ule(float %a, float %b) nounwind {
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ule:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: slti a0, a0, 1
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ule:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: slti a0, a0, 1
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp ule float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -285,6 +595,26 @@ define i32 @fcmp_une(float %a, float %b) nounwind {
; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_une:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __nesf2 at plt
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_une:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __nesf2 at plt
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp une float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -310,6 +640,26 @@ define i32 @fcmp_uno(float %a, float %b) nounwind {
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_uno:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_uno:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __unordsf2 at plt
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fcmp uno float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -325,6 +675,16 @@ define i32 @fcmp_true(float %a, float %b) nounwind {
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi a0, zero, 1
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: fcmp_true:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a0, zero, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_true:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a0, zero, 1
+; RV64I-NEXT: ret
%1 = fcmp true float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
diff --git a/llvm/test/CodeGen/RISCV/float-frem.ll b/llvm/test/CodeGen/RISCV/float-frem.ll
index 10e2ebfad238..ce63cb48c9fc 100644
--- a/llvm/test/CodeGen/RISCV/float-frem.ll
+++ b/llvm/test/CodeGen/RISCV/float-frem.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
define float @frem_f32(float %a, float %b) nounwind {
; RV32IF-LABEL: frem_f32:
@@ -22,6 +26,24 @@ define float @frem_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV32I-LABEL: frem_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call fmodf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: frem_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fmodf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = frem float %a, %b
ret float %1
}
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
index a340d31a5f39..e5b2ce6ea996 100644
--- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -7,6 +7,10 @@
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
+; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
+; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
declare float @llvm.sqrt.f32(float)
@@ -24,6 +28,15 @@ define float @sqrt_f32(float %a) nounwind {
; RV64IF-NEXT: fsqrt.s ft0, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: sqrt_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call sqrtf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.sqrt.f32(float %a)
ret float %1
}
@@ -49,6 +62,16 @@ define float @powi_f32(float %a, i32 %b) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: powi_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sext.w a1, a1
+; RV64I-NEXT: call __powisf2 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.powi.f32.i32(float %a, i32 %b)
ret float %1
}
@@ -73,6 +96,15 @@ define float @sin_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: sin_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call sinf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.sin.f32(float %a)
ret float %1
}
@@ -97,6 +129,15 @@ define float @cos_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: cos_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call cosf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.cos.f32(float %a)
ret float %1
}
@@ -142,6 +183,26 @@ define float @sincos_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: sincos_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: call sinf at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call cosf at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = call float @llvm.sin.f32(float %a)
%2 = call float @llvm.cos.f32(float %a)
%3 = fadd float %1, %2
@@ -168,6 +229,15 @@ define float @pow_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: pow_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call powf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.pow.f32(float %a, float %b)
ret float %1
}
@@ -192,6 +262,15 @@ define float @exp_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: exp_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call expf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.exp.f32(float %a)
ret float %1
}
@@ -216,6 +295,15 @@ define float @exp2_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: exp2_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call exp2f at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.exp2.f32(float %a)
ret float %1
}
@@ -240,6 +328,15 @@ define float @log_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: log_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call logf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.log.f32(float %a)
ret float %1
}
@@ -264,6 +361,15 @@ define float @log10_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: log10_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call log10f at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.log10.f32(float %a)
ret float %1
}
@@ -288,6 +394,15 @@ define float @log2_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: log2_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call log2f at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.log2.f32(float %a)
ret float %1
}
@@ -312,6 +427,15 @@ define float @fma_f32(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: fma_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.fma.f32(float %a, float %b, float %c)
ret float %1
}
@@ -336,6 +460,20 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: fmuladd_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
ret float %1
}
@@ -356,6 +494,13 @@ define float @fabs_f32(float %a) nounwind {
; RV64IF-NEXT: addiw a1, a1, -1
; RV64IF-NEXT: and a0, a0, a1
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: fabs_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
%1 = call float @llvm.fabs.f32(float %a)
ret float %1
}
@@ -378,6 +523,15 @@ define float @minnum_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fmin.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: minnum_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fminf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.minnum.f32(float %a, float %b)
ret float %1
}
@@ -400,6 +554,15 @@ define float @maxnum_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fmax.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: maxnum_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call fmaxf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.maxnum.f32(float %a, float %b)
ret float %1
}
@@ -439,6 +602,15 @@ define float @copysign_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fsgnj.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: copysign_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a2, 524288
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: addiw a2, a2, -1
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
%1 = call float @llvm.copysign.f32(float %a, float %b)
ret float %1
}
@@ -463,6 +635,15 @@ define float @floor_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: floor_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call floorf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.floor.f32(float %a)
ret float %1
}
@@ -487,6 +668,15 @@ define float @ceil_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: ceil_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call ceilf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.ceil.f32(float %a)
ret float %1
}
@@ -511,6 +701,15 @@ define float @trunc_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: trunc_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call truncf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.trunc.f32(float %a)
ret float %1
}
@@ -535,6 +734,15 @@ define float @rint_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: rint_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call rintf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.rint.f32(float %a)
ret float %1
}
@@ -559,6 +767,15 @@ define float @nearbyint_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: nearbyint_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call nearbyintf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.nearbyint.f32(float %a)
ret float %1
}
@@ -583,6 +800,15 @@ define float @round_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: round_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call roundf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.round.f32(float %a)
ret float %1
}
@@ -607,6 +833,15 @@ define float @roundeven_f32(float %a) nounwind {
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: roundeven_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call roundevenf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call float @llvm.roundeven.f32(float %a)
ret float %1
}
@@ -625,6 +860,15 @@ define iXLen @lrint_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: lrint_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call lrintf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call iXLen @llvm.lrint.iXLen.f32(float %a)
ret iXLen %1
}
@@ -643,6 +887,15 @@ define iXLen @lround_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0, rmm
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: lround_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call lroundf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call iXLen @llvm.lround.iXLen.f32(float %a)
ret iXLen %1
}
@@ -664,6 +917,15 @@ define i64 @llrint_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: llrint_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call llrintf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call i64 @llvm.llrint.i64.f32(float %a)
ret i64 %1
}
@@ -685,6 +947,15 @@ define i64 @llround_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0, rmm
; RV64IF-NEXT: ret
+;
+; RV64I-LABEL: llround_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call llroundf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call i64 @llvm.llround.i64.f32(float %a)
ret i64 %1
}
diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll
index ad4978e117cf..07e994b11bfd 100644
--- a/llvm/test/CodeGen/RISCV/half-arith.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith.ll
@@ -1,10 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
-; RUN: -target-abi ilp32f < %s \
-; RUN: | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
-; RUN: -target-abi lp64f < %s \
-; RUN: | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
; These tests are each targeted at a particular RISC-V FPU instruction. Most
; other files in this folder exercise LLVM IR instructions that don't directly
@@ -20,6 +22,58 @@ define half @fadd_s(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fadd_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fadd_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fadd half %a, %b
ret half %1
}
@@ -34,6 +88,58 @@ define half @fsub_s(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fsub.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fsub_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __subsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsub_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __subsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fsub half %a, %b
ret half %1
}
@@ -48,6 +154,58 @@ define half @fmul_s(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmul.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fmul_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmul_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fmul half %a, %b
ret half %1
}
@@ -62,6 +220,58 @@ define half @fdiv_s(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fdiv.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fdiv_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __divsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fdiv_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __divsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fdiv half %a, %b
ret half %1
}
@@ -78,6 +288,34 @@ define half @fsqrt_s(half %a) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fsqrt.h fa0, fa0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fsqrt_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call sqrtf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsqrt_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call sqrtf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call half @llvm.sqrt.f16(half %a)
ret half %1
}
@@ -94,6 +332,26 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fsgnj_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 1048568
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: lui a2, 8
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsgnj_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a2, 1048568
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: lui a2, 8
+; RV64I-NEXT: addiw a2, a2, -1
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
%1 = call half @llvm.copysign.f16(half %a, half %b)
ret half %1
}
@@ -114,6 +372,68 @@ define i32 @fneg_s(half %a, half %b) nounwind {
; RV64IZFH-NEXT: fneg.h ft1, ft0
; RV64IZFH-NEXT: feq.h a0, ft0, ft1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fneg_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s1, a1, -1
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lui a0, 524288
+; RV32I-NEXT: xor a0, s0, a0
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __eqsf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fneg_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s1, a1, -1
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lui a0, 524288
+; RV64I-NEXT: xor a0, s0, a0
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __eqsf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fadd half %a, %a
%2 = fneg half %1
%3 = fcmp oeq half %1, %2
@@ -135,6 +455,86 @@ define half @fsgnjn_s(half %a, half %b) nounwind {
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
; RV64IZFH-NEXT: fsgnjn.h fa0, fa0, ft0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fsgnjn_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi s0, a0, -1
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s3, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lui a1, 1048568
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: lui a1, 8
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a1, s2, a1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fsgnjn_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: lui a0, 16
+; RV64I-NEXT: addiw s0, a0, -1
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s3, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: lui a1, 1048568
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: lui a1, 8
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a1, s2, a1
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%1 = fadd half %a, %b
%2 = fneg half %1
%3 = call half @llvm.copysign.f16(half %a, half %2)
@@ -159,6 +559,82 @@ define half @fabs_s(half %a, half %b) nounwind {
; RV64IZFH-NEXT: fabs.h ft1, ft0
; RV64IZFH-NEXT: fadd.h fa0, ft1, ft0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fabs_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s1, a1, -1
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s2, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lui a0, 524288
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: and a0, s0, a0
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fabs_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s1, a1, -1
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s2, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lui a0, 524288
+; RV64I-NEXT: addiw a0, a0, -1
+; RV64I-NEXT: and a0, s0, a0
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fadd half %a, %b
%2 = call half @llvm.fabs.f16(half %1)
%3 = fadd half %2, %1
@@ -177,6 +653,58 @@ define half @fmin_s(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmin.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fmin_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call fminf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmin_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call fminf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = call half @llvm.minnum.f16(half %a, half %b)
ret half %1
}
@@ -193,6 +721,58 @@ define half @fmax_s(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmax.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fmax_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call fmaxf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmax_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call fmaxf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = call half @llvm.maxnum.f16(half %a, half %b)
ret half %1
}
@@ -207,6 +787,58 @@ define i32 @feq_s(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: feq_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __eqsf2 at plt
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: feq_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __eqsf2 at plt
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fcmp oeq half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -222,6 +854,58 @@ define i32 @flt_s(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: flt_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __ltsf2 at plt
+; RV32I-NEXT: slti a0, a0, 0
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: flt_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __ltsf2 at plt
+; RV64I-NEXT: slti a0, a0, 0
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fcmp olt half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -237,6 +921,58 @@ define i32 @fle_s(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fle_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __lesf2 at plt
+; RV32I-NEXT: slti a0, a0, 1
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fle_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __lesf2 at plt
+; RV64I-NEXT: slti a0, a0, 1
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = fcmp ole half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -254,6 +990,72 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fmadd_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a2
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: and a0, s1, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmadd_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: and a0, s1, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: mv a0, s3
+; RV64I-NEXT: mv a1, s1
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%1 = call half @llvm.fma.f16(half %a, half %b, half %c)
ret half %1
}
@@ -272,6 +1074,98 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fmsub_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi s0, a0, -1
+; RV32I-NEXT: and a0, a2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: and a0, s1, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s4, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmsub_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: lui a0, 16
+; RV64I-NEXT: addiw s0, a0, -1
+; RV64I-NEXT: and a0, a2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: and a0, s1, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s4, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: mv a0, s3
+; RV64I-NEXT: mv a1, s1
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%c_ = fadd half 0.0, %c ; avoid negation using xor
%negc = fsub half -0.0, %c_
%1 = call half @llvm.fma.f16(half %a, half %b, half %negc)
@@ -294,6 +1188,122 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fnmadd_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s3, a2
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s1, a1, -1
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: and a0, s3, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s4, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: lui s4, 524288
+; RV32I-NEXT: xor a0, a0, s4
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: and a0, s0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: xor a0, a0, s4
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: and a0, s2, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: and a0, s3, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s4, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmadd_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s3, a2
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s1, a1, -1
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: and a0, s3, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s4, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: lui s4, 524288
+; RV64I-NEXT: xor a0, a0, s4
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: and a0, s0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: xor a0, a0, s4
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: and a0, s2, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: and a0, s3, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s4, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, s2
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%a_ = fadd half 0.0, %a
%c_ = fadd half 0.0, %c
%nega = fsub half -0.0, %a_
@@ -318,6 +1328,122 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fnmadd_s_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s3, a2
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi s1, a0, -1
+; RV32I-NEXT: and a0, a1, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: and a0, s3, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s4, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: lui s4, 524288
+; RV32I-NEXT: xor a0, a0, s4
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: and a0, s0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: xor a0, a0, s4
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: and a0, s2, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: and a0, s3, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s4, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmadd_s_2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s3, a2
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: lui a0, 16
+; RV64I-NEXT: addiw s1, a0, -1
+; RV64I-NEXT: and a0, a1, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: and a0, s3, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s4, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: lui s4, 524288
+; RV64I-NEXT: xor a0, a0, s4
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: and a0, s0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: xor a0, a0, s4
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: and a0, s2, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: and a0, s3, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s4, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%b_ = fadd half 0.0, %b
%c_ = fadd half 0.0, %c
%negb = fsub half -0.0, %b_
@@ -340,6 +1466,96 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; RV64IZFH-NEXT: fadd.h ft0, fa0, ft0
; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fnmsub_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a2
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: and a0, s1, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s4, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a2, s1
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmsub_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: and a0, s1, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s4, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a2, s1
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%a_ = fadd half 0.0, %a
%nega = fsub half -0.0, %a_
%1 = call half @llvm.fma.f16(half %nega, half %b, half %c)
@@ -360,6 +1576,98 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fnmsub_s_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a2
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi s0, a0, -1
+; RV32I-NEXT: and a0, a1, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: and a0, s1, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s4, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: mv a2, s1
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmsub_s_2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: lui a0, 16
+; RV64I-NEXT: addiw s0, a0, -1
+; RV64I-NEXT: and a0, a1, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: and a0, s1, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s4, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s3
+; RV64I-NEXT: mv a2, s1
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%b_ = fadd half 0.0, %b
%negb = fsub half -0.0, %b_
%1 = call half @llvm.fma.f16(half %a, half %negb, half %c)
@@ -376,6 +1684,82 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fmadd_s_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a2
+; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s1, a1, -1
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s3, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s2, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: and a0, s0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmadd_s_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s1, a1, -1
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s3, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s2, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: and a0, s0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, s2
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%1 = fmul contract half %a, %b
%2 = fadd contract half %1, %c
ret half %2
@@ -395,6 +1779,94 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fmsub_s_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi s0, a0, -1
+; RV32I-NEXT: and a0, a2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: and a0, s1, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s3, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __subsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmsub_s_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: lui a0, 16
+; RV64I-NEXT: addiw s0, a0, -1
+; RV64I-NEXT: and a0, a2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: and a0, s1, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s3, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __subsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%c_ = fadd half 0.0, %c ; avoid negation using xor
%1 = fmul contract half %a, %b
%2 = fsub contract half %1, %c_
@@ -419,6 +1891,132 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fnmadd_s_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a2
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s1, a1, -1
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: and a0, s0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: and a0, s2, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: and a0, s3, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s4, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s2, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: and a0, s0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: call __subsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmadd_s_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s1, a1, -1
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: and a0, s0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: and a0, s2, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: and a0, s3, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s4, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s2, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: and a0, s0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, s2
+; RV64I-NEXT: call __subsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%a_ = fadd half 0.0, %a ; avoid negation using xor
%b_ = fadd half 0.0, %b ; avoid negation using xor
%c_ = fadd half 0.0, %c ; avoid negation using xor
@@ -444,6 +2042,108 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
; RV64IZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fnmsub_s_contract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a2
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: and a0, s1, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s3, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: and a0, s1, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: and a0, s1, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: call __subsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fnmsub_s_contract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: and a0, s1, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s3, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: and a0, s1, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s3
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: and a0, s1, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: call __subsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%a_ = fadd half 0.0, %a ; avoid negation using xor
%b_ = fadd half 0.0, %b ; avoid negation using xor
%1 = fmul contract half %a_, %b_
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index eddbcffdb1b1..7874109d4c60 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -1,12 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
-; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh -verify-machineinstrs \
-; RUN: -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh -verify-machineinstrs \
+; RUN: -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh -verify-machineinstrs \
; RUN: -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs \
+; RUN: < %s | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs \
+; RUN: < %s | FileCheck -check-prefix=RV64I %s
define i16 @fcvt_si_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_si_h:
@@ -14,20 +18,46 @@ define i16 @fcvt_si_h(half %a) nounwind {
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_si_h:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_si_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_si_h:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_si_h:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_si_h:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call __fixsfsi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_si_h:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call __fixsfdi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptosi half %a to i16
ret i16 %1
}
@@ -51,24 +81,6 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_si_h_sat:
-; RV32IDZFH: # %bb.0: # %start
-; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0
-; RV32IDZFH-NEXT: feq.s a0, ft0, ft0
-; RV32IDZFH-NEXT: bnez a0, .LBB1_2
-; RV32IDZFH-NEXT: # %bb.1: # %start
-; RV32IDZFH-NEXT: mv a0, zero
-; RV32IDZFH-NEXT: ret
-; RV32IDZFH-NEXT: .LBB1_2:
-; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
-; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IDZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0)
-; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_si_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h ft0, fa0
@@ -87,6 +99,24 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_si_h_sat:
+; RV32IDZFH: # %bb.0: # %start
+; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0
+; RV32IDZFH-NEXT: feq.s a0, ft0, ft0
+; RV32IDZFH-NEXT: bnez a0, .LBB1_2
+; RV32IDZFH-NEXT: # %bb.1: # %start
+; RV32IDZFH-NEXT: mv a0, zero
+; RV32IDZFH-NEXT: ret
+; RV32IDZFH-NEXT: .LBB1_2:
+; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
+; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
+; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_1)
+; RV32IDZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0)
+; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1
+; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2
+; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_si_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0
@@ -104,6 +134,104 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2
; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_si_h_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lui a1, 815104
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __fixsfsi at plt
+; RV32I-NEXT: mv s1, zero
+; RV32I-NEXT: lui s3, 1048568
+; RV32I-NEXT: bltz s2, .LBB1_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: .LBB1_2: # %start
+; RV32I-NEXT: lui a0, 290816
+; RV32I-NEXT: addi a1, a0, -512
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: bge s1, a0, .LBB1_4
+; RV32I-NEXT: # %bb.3:
+; RV32I-NEXT: lui a0, 8
+; RV32I-NEXT: addi s3, a0, -1
+; RV32I-NEXT: .LBB1_4: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: bne a0, s1, .LBB1_6
+; RV32I-NEXT: # %bb.5: # %start
+; RV32I-NEXT: mv s1, s3
+; RV32I-NEXT: .LBB1_6: # %start
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_si_h_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lui a1, 815104
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixsfdi at plt
+; RV64I-NEXT: mv s1, zero
+; RV64I-NEXT: lui s3, 1048568
+; RV64I-NEXT: bltz s2, .LBB1_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: .LBB1_2: # %start
+; RV64I-NEXT: lui a0, 290816
+; RV64I-NEXT: addiw a1, a0, -512
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: bge s1, a0, .LBB1_4
+; RV64I-NEXT: # %bb.3:
+; RV64I-NEXT: lui a0, 8
+; RV64I-NEXT: addiw s3, a0, -1
+; RV64I-NEXT: .LBB1_4: # %start
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unordsf2 at plt
+; RV64I-NEXT: bne a0, s1, .LBB1_6
+; RV64I-NEXT: # %bb.5: # %start
+; RV64I-NEXT: mv s1, s3
+; RV64I-NEXT: .LBB1_6: # %start
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
start:
%0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
ret i16 %0
@@ -116,20 +244,46 @@ define i16 @fcvt_ui_h(half %a) nounwind {
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_ui_h:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_ui_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_ui_h:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_ui_h:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_ui_h:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call __fixunssfsi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_ui_h:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call __fixunssfdi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptoui half %a to i16
ret i16 %1
}
@@ -148,16 +302,6 @@ define i32 @fcvt_ui_h_multiple_use(half %x, i32* %y) {
; RV32IZFH-NEXT: .LBB3_2:
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_ui_h_multiple_use:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.wu.h a1, fa0, rtz
-; RV32IDZFH-NEXT: addi a0, zero, 1
-; RV32IDZFH-NEXT: beqz a1, .LBB3_2
-; RV32IDZFH-NEXT: # %bb.1:
-; RV32IDZFH-NEXT: mv a0, a1
-; RV32IDZFH-NEXT: .LBB3_2:
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_ui_h_multiple_use:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
@@ -168,6 +312,16 @@ define i32 @fcvt_ui_h_multiple_use(half %x, i32* %y) {
; RV64IZFH-NEXT: .LBB3_2:
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_ui_h_multiple_use:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.wu.h a1, fa0, rtz
+; RV32IDZFH-NEXT: addi a0, zero, 1
+; RV32IDZFH-NEXT: beqz a1, .LBB3_2
+; RV32IDZFH-NEXT: # %bb.1:
+; RV32IDZFH-NEXT: mv a0, a1
+; RV32IDZFH-NEXT: .LBB3_2:
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_ui_h_multiple_use:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.wu.h a1, fa0, rtz
@@ -177,6 +331,49 @@ define i32 @fcvt_ui_h_multiple_use(half %x, i32* %y) {
; RV64IDZFH-NEXT: mv a0, a1
; RV64IDZFH-NEXT: .LBB3_2:
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_ui_h_multiple_use:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call __fixunssfsi at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: addi a0, zero, 1
+; RV32I-NEXT: beqz a1, .LBB3_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB3_2:
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_ui_h_multiple_use:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call __fixunssfdi at plt
+; RV64I-NEXT: sext.w a2, a0
+; RV64I-NEXT: addi a1, zero, 1
+; RV64I-NEXT: beqz a2, .LBB3_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: .LBB3_2:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%a = fptoui half %x to i32
%b = icmp eq i32 %a, 0
%c = select i1 %b, i32 1, i32 %a
@@ -195,17 +392,6 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV32IZFH-NEXT: fcvt.wu.s a0, ft0, rtz
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_ui_h_sat:
-; RV32IDZFH: # %bb.0: # %start
-; RV32IDZFH-NEXT: lui a0, %hi(.LCPI4_0)
-; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
-; RV32IDZFH-NEXT: fcvt.s.h ft1, fa0
-; RV32IDZFH-NEXT: fmv.w.x ft2, zero
-; RV32IDZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV32IDZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV32IDZFH-NEXT: fcvt.wu.s a0, ft0, rtz
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_ui_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: lui a0, %hi(.LCPI4_0)
@@ -217,6 +403,17 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64IZFH-NEXT: fcvt.lu.s a0, ft0, rtz
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_ui_h_sat:
+; RV32IDZFH: # %bb.0: # %start
+; RV32IDZFH-NEXT: lui a0, %hi(.LCPI4_0)
+; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
+; RV32IDZFH-NEXT: fcvt.s.h ft1, fa0
+; RV32IDZFH-NEXT: fmv.w.x ft2, zero
+; RV32IDZFH-NEXT: fmax.s ft1, ft1, ft2
+; RV32IDZFH-NEXT: fmin.s ft0, ft1, ft0
+; RV32IDZFH-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_ui_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI4_0)
@@ -227,6 +424,86 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64IDZFH-NEXT: fmin.s ft0, ft1, ft0
; RV64IDZFH-NEXT: fcvt.lu.s a0, ft0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_ui_h_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s2, a1, -1
+; RV32I-NEXT: and a0, a0, s2
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __fixunssfsi at plt
+; RV32I-NEXT: mv s3, zero
+; RV32I-NEXT: bltz s0, .LBB4_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: .LBB4_2: # %start
+; RV32I-NEXT: lui a0, 292864
+; RV32I-NEXT: addi a1, a0, -256
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: bgtz a0, .LBB4_4
+; RV32I-NEXT: # %bb.3: # %start
+; RV32I-NEXT: mv s2, s3
+; RV32I-NEXT: .LBB4_4: # %start
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_ui_h_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s2, a1, -1
+; RV64I-NEXT: and a0, a0, s2
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __fixunssfdi at plt
+; RV64I-NEXT: mv s3, zero
+; RV64I-NEXT: bltz s0, .LBB4_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: .LBB4_2: # %start
+; RV64I-NEXT: lui a0, 292864
+; RV64I-NEXT: addiw a1, a0, -256
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: bgtz a0, .LBB4_4
+; RV64I-NEXT: # %bb.3: # %start
+; RV64I-NEXT: mv s2, s3
+; RV64I-NEXT: .LBB4_4: # %start
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
start:
%0 = tail call i16 @llvm.fptoui.sat.i16.f16(half %a)
ret i16 %0
@@ -239,20 +516,46 @@ define i32 @fcvt_w_h(half %a) nounwind {
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_w_h:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_w_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_w_h:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_w_h:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_w_h:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call __fixsfsi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_w_h:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call __fixsfdi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptosi half %a to i32
ret i32 %1
}
@@ -269,17 +572,6 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_w_h_sat:
-; RV32IDZFH: # %bb.0: # %start
-; RV32IDZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IDZFH-NEXT: bnez a0, .LBB6_2
-; RV32IDZFH-NEXT: # %bb.1: # %start
-; RV32IDZFH-NEXT: mv a0, zero
-; RV32IDZFH-NEXT: ret
-; RV32IDZFH-NEXT: .LBB6_2:
-; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_w_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
@@ -291,6 +583,17 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_w_h_sat:
+; RV32IDZFH: # %bb.0: # %start
+; RV32IDZFH-NEXT: feq.h a0, fa0, fa0
+; RV32IDZFH-NEXT: bnez a0, .LBB6_2
+; RV32IDZFH-NEXT: # %bb.1: # %start
+; RV32IDZFH-NEXT: mv a0, zero
+; RV32IDZFH-NEXT: ret
+; RV32IDZFH-NEXT: .LBB6_2:
+; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_w_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
@@ -301,6 +604,108 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV64IDZFH-NEXT: .LBB6_2:
; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_w_h_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lui a1, 847872
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __fixsfsi at plt
+; RV32I-NEXT: mv s1, zero
+; RV32I-NEXT: lui s4, 524288
+; RV32I-NEXT: lui s3, 524288
+; RV32I-NEXT: bltz s2, .LBB6_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: .LBB6_2: # %start
+; RV32I-NEXT: lui a0, 323584
+; RV32I-NEXT: addi a1, a0, -1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: bge s1, a0, .LBB6_4
+; RV32I-NEXT: # %bb.3:
+; RV32I-NEXT: addi s3, s4, -1
+; RV32I-NEXT: .LBB6_4: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: bne a0, s1, .LBB6_6
+; RV32I-NEXT: # %bb.5: # %start
+; RV32I-NEXT: mv s1, s3
+; RV32I-NEXT: .LBB6_6: # %start
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_w_h_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lui a1, 847872
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixsfdi at plt
+; RV64I-NEXT: mv s1, zero
+; RV64I-NEXT: lui s4, 524288
+; RV64I-NEXT: lui s3, 524288
+; RV64I-NEXT: bltz s2, .LBB6_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: .LBB6_2: # %start
+; RV64I-NEXT: lui a0, 323584
+; RV64I-NEXT: addiw a1, a0, -1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: bge s1, a0, .LBB6_4
+; RV64I-NEXT: # %bb.3:
+; RV64I-NEXT: addiw s3, s4, -1
+; RV64I-NEXT: .LBB6_4: # %start
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unordsf2 at plt
+; RV64I-NEXT: bne a0, s1, .LBB6_6
+; RV64I-NEXT: # %bb.5: # %start
+; RV64I-NEXT: mv s1, s3
+; RV64I-NEXT: .LBB6_6: # %start
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
start:
%0 = tail call i32 @llvm.fptosi.sat.i32.f16(half %a)
ret i32 %0
@@ -313,20 +718,46 @@ define i32 @fcvt_wu_h(half %a) nounwind {
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_wu_h:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_wu_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_wu_h:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_wu_h:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_wu_h:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call __fixunssfsi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_wu_h:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call __fixunssfdi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptoui half %a to i32
ret i32 %1
}
@@ -343,17 +774,6 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_wu_h_sat:
-; RV32IDZFH: # %bb.0: # %start
-; RV32IDZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IDZFH-NEXT: bnez a0, .LBB8_2
-; RV32IDZFH-NEXT: # %bb.1: # %start
-; RV32IDZFH-NEXT: mv a0, zero
-; RV32IDZFH-NEXT: ret
-; RV32IDZFH-NEXT: .LBB8_2:
-; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_wu_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
@@ -365,6 +785,17 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_wu_h_sat:
+; RV32IDZFH: # %bb.0: # %start
+; RV32IDZFH-NEXT: feq.h a0, fa0, fa0
+; RV32IDZFH-NEXT: bnez a0, .LBB8_2
+; RV32IDZFH-NEXT: # %bb.1: # %start
+; RV32IDZFH-NEXT: mv a0, zero
+; RV32IDZFH-NEXT: ret
+; RV32IDZFH-NEXT: .LBB8_2:
+; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_wu_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
@@ -375,6 +806,84 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64IDZFH-NEXT: .LBB8_2:
; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_wu_h_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __fixunssfsi at plt
+; RV32I-NEXT: mv s2, zero
+; RV32I-NEXT: bltz s1, .LBB8_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: .LBB8_2: # %start
+; RV32I-NEXT: lui a0, 325632
+; RV32I-NEXT: addi a1, a0, -1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: addi a0, zero, -1
+; RV32I-NEXT: bgtz a1, .LBB8_4
+; RV32I-NEXT: # %bb.3: # %start
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: .LBB8_4: # %start
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_wu_h_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixunssfdi at plt
+; RV64I-NEXT: mv s1, zero
+; RV64I-NEXT: bltz s2, .LBB8_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: .LBB8_2: # %start
+; RV64I-NEXT: lui a0, 325632
+; RV64I-NEXT: addiw a1, a0, -1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: blez a0, .LBB8_4
+; RV64I-NEXT: # %bb.3:
+; RV64I-NEXT: addi a0, zero, -1
+; RV64I-NEXT: srli s1, a0, 32
+; RV64I-NEXT: .LBB8_4: # %start
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
start:
%0 = tail call i32 @llvm.fptoui.sat.i32.f16(half %a)
ret i32 %0
@@ -391,6 +900,11 @@ define i64 @fcvt_l_h(half %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
+; RV64IZFH-LABEL: fcvt_l_h:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
+; RV64IZFH-NEXT: ret
+;
; RV32IDZFH-LABEL: fcvt_l_h:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
@@ -400,15 +914,36 @@ define i64 @fcvt_l_h(half %a) nounwind {
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
-; RV64IZFH-LABEL: fcvt_l_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
-; RV64IZFH-NEXT: ret
-;
; RV64IDZFH-LABEL: fcvt_l_h:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_l_h:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call __fixsfdi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_l_h:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call __fixsfdi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptosi half %a to i64
ret i64 %1
}
@@ -470,6 +1005,17 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32IZFH-NEXT: beqz a2, .LBB10_7
; RV32IZFH-NEXT: j .LBB10_8
;
+; RV64IZFH-LABEL: fcvt_l_h_sat:
+; RV64IZFH: # %bb.0: # %start
+; RV64IZFH-NEXT: feq.h a0, fa0, fa0
+; RV64IZFH-NEXT: bnez a0, .LBB10_2
+; RV64IZFH-NEXT: # %bb.1: # %start
+; RV64IZFH-NEXT: mv a0, zero
+; RV64IZFH-NEXT: ret
+; RV64IZFH-NEXT: .LBB10_2:
+; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
+; RV64IZFH-NEXT: ret
+;
; RV32IDZFH-LABEL: fcvt_l_h_sat:
; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: addi sp, sp, -16
@@ -526,17 +1072,6 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32IDZFH-NEXT: beqz a2, .LBB10_7
; RV32IDZFH-NEXT: j .LBB10_8
;
-; RV64IZFH-LABEL: fcvt_l_h_sat:
-; RV64IZFH: # %bb.0: # %start
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB10_2
-; RV64IZFH-NEXT: # %bb.1: # %start
-; RV64IZFH-NEXT: mv a0, zero
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB10_2:
-; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
-; RV64IZFH-NEXT: ret
-;
; RV64IDZFH-LABEL: fcvt_l_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
@@ -547,6 +1082,141 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV64IDZFH-NEXT: .LBB10_2:
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_l_h_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lui a1, 913408
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __fixsfdi at plt
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: mv s1, zero
+; RV32I-NEXT: mv s5, zero
+; RV32I-NEXT: bltz s3, .LBB10_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s5, a0
+; RV32I-NEXT: .LBB10_2: # %start
+; RV32I-NEXT: lui a0, 389120
+; RV32I-NEXT: addi s4, a0, -1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s4
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: addi s6, zero, -1
+; RV32I-NEXT: blt s1, a0, .LBB10_4
+; RV32I-NEXT: # %bb.3: # %start
+; RV32I-NEXT: mv s6, s5
+; RV32I-NEXT: .LBB10_4: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: mv s3, s1
+; RV32I-NEXT: bne a0, s1, .LBB10_6
+; RV32I-NEXT: # %bb.5: # %start
+; RV32I-NEXT: mv s3, s6
+; RV32I-NEXT: .LBB10_6: # %start
+; RV32I-NEXT: lui a1, 913408
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: lui s6, 524288
+; RV32I-NEXT: lui s5, 524288
+; RV32I-NEXT: blt a0, s1, .LBB10_8
+; RV32I-NEXT: # %bb.7: # %start
+; RV32I-NEXT: mv s5, s2
+; RV32I-NEXT: .LBB10_8: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s4
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: bge s1, a0, .LBB10_10
+; RV32I-NEXT: # %bb.9:
+; RV32I-NEXT: addi s5, s6, -1
+; RV32I-NEXT: .LBB10_10: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s0
+; RV32I-NEXT: call __unordsf2 at plt
+; RV32I-NEXT: bne a0, s1, .LBB10_12
+; RV32I-NEXT: # %bb.11: # %start
+; RV32I-NEXT: mv s1, s5
+; RV32I-NEXT: .LBB10_12: # %start
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_l_h_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lui a1, 913408
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixsfdi at plt
+; RV64I-NEXT: mv s1, zero
+; RV64I-NEXT: addi s4, zero, -1
+; RV64I-NEXT: bltz s3, .LBB10_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: j .LBB10_3
+; RV64I-NEXT: .LBB10_2:
+; RV64I-NEXT: slli s2, s4, 63
+; RV64I-NEXT: .LBB10_3: # %start
+; RV64I-NEXT: lui a0, 389120
+; RV64I-NEXT: addiw a1, a0, -1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: bge s1, a0, .LBB10_5
+; RV64I-NEXT: # %bb.4:
+; RV64I-NEXT: srli s2, s4, 1
+; RV64I-NEXT: .LBB10_5: # %start
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: mv a1, s0
+; RV64I-NEXT: call __unordsf2 at plt
+; RV64I-NEXT: bne a0, s1, .LBB10_7
+; RV64I-NEXT: # %bb.6: # %start
+; RV64I-NEXT: mv s1, s2
+; RV64I-NEXT: .LBB10_7: # %start
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
start:
%0 = tail call i64 @llvm.fptosi.sat.i64.f16(half %a)
ret i64 %0
@@ -563,6 +1233,11 @@ define i64 @fcvt_lu_h(half %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
+; RV64IZFH-LABEL: fcvt_lu_h:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
+; RV64IZFH-NEXT: ret
+;
; RV32IDZFH-LABEL: fcvt_lu_h:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
@@ -572,15 +1247,36 @@ define i64 @fcvt_lu_h(half %a) nounwind {
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
-; RV64IZFH-LABEL: fcvt_lu_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
-; RV64IZFH-NEXT: ret
-;
; RV64IDZFH-LABEL: fcvt_lu_h:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_lu_h:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call __fixunssfdi at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_lu_h:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call __fixunssfdi at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptoui half %a to i64
ret i64 %1
}
@@ -629,6 +1325,17 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV32IZFH-NEXT: beqz a4, .LBB12_5
; RV32IZFH-NEXT: j .LBB12_6
;
+; RV64IZFH-LABEL: fcvt_lu_h_sat:
+; RV64IZFH: # %bb.0: # %start
+; RV64IZFH-NEXT: feq.h a0, fa0, fa0
+; RV64IZFH-NEXT: bnez a0, .LBB12_2
+; RV64IZFH-NEXT: # %bb.1: # %start
+; RV64IZFH-NEXT: mv a0, zero
+; RV64IZFH-NEXT: ret
+; RV64IZFH-NEXT: .LBB12_2:
+; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
+; RV64IZFH-NEXT: ret
+;
; RV32IDZFH-LABEL: fcvt_lu_h_sat:
; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: addi sp, sp, -16
@@ -672,17 +1379,6 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV32IDZFH-NEXT: beqz a4, .LBB12_5
; RV32IDZFH-NEXT: j .LBB12_6
;
-; RV64IZFH-LABEL: fcvt_lu_h_sat:
-; RV64IZFH: # %bb.0: # %start
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB12_2
-; RV64IZFH-NEXT: # %bb.1: # %start
-; RV64IZFH-NEXT: mv a0, zero
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB12_2:
-; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
-; RV64IZFH-NEXT: ret
-;
; RV64IDZFH-LABEL: fcvt_lu_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
@@ -693,6 +1389,109 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV64IDZFH-NEXT: .LBB12_2:
; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_lu_h_sat:
+; RV32I: # %bb.0: # %start
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __fixunssfdi at plt
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: mv s5, zero
+; RV32I-NEXT: bltz s1, .LBB12_2
+; RV32I-NEXT: # %bb.1: # %start
+; RV32I-NEXT: mv s5, a0
+; RV32I-NEXT: .LBB12_2: # %start
+; RV32I-NEXT: lui a0, 391168
+; RV32I-NEXT: addi s1, a0, -1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: addi s3, zero, -1
+; RV32I-NEXT: addi s4, zero, -1
+; RV32I-NEXT: bgtz a0, .LBB12_4
+; RV32I-NEXT: # %bb.3: # %start
+; RV32I-NEXT: mv s4, s5
+; RV32I-NEXT: .LBB12_4: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __gesf2 at plt
+; RV32I-NEXT: mv s5, zero
+; RV32I-NEXT: bltz a0, .LBB12_6
+; RV32I-NEXT: # %bb.5: # %start
+; RV32I-NEXT: mv s5, s2
+; RV32I-NEXT: .LBB12_6: # %start
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call __gtsf2 at plt
+; RV32I-NEXT: bgtz a0, .LBB12_8
+; RV32I-NEXT: # %bb.7: # %start
+; RV32I-NEXT: mv s3, s5
+; RV32I-NEXT: .LBB12_8: # %start
+; RV32I-NEXT: mv a0, s4
+; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_lu_h_sat:
+; RV64I: # %bb.0: # %start
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: mv a1, zero
+; RV64I-NEXT: call __gesf2 at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __fixunssfdi at plt
+; RV64I-NEXT: mv s2, zero
+; RV64I-NEXT: bltz s1, .LBB12_2
+; RV64I-NEXT: # %bb.1: # %start
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: .LBB12_2: # %start
+; RV64I-NEXT: lui a0, 391168
+; RV64I-NEXT: addiw a1, a0, -1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __gtsf2 at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: addi a0, zero, -1
+; RV64I-NEXT: bgtz a1, .LBB12_4
+; RV64I-NEXT: # %bb.3: # %start
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: .LBB12_4: # %start
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
start:
%0 = tail call i64 @llvm.fptoui.sat.i64.f16(half %a)
ret i64 %0
@@ -707,13 +1506,6 @@ define half @fcvt_h_si(i16 %a) nounwind {
; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_si:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: slli a0, a0, 16
-; RV32IDZFH-NEXT: srai a0, a0, 16
-; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_si:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: slli a0, a0, 48
@@ -721,12 +1513,43 @@ define half @fcvt_h_si(i16 %a) nounwind {
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_si:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: slli a0, a0, 16
+; RV32IDZFH-NEXT: srai a0, a0, 16
+; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_si:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: slli a0, a0, 48
; RV64IDZFH-NEXT: srai a0, a0, 48
; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_si:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srai a0, a0, 16
+; RV32I-NEXT: call __floatsisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_si:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srai a0, a0, 48
+; RV64I-NEXT: call __floatsisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i16 %a to half
ret half %1
}
@@ -737,20 +1560,40 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind {
; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_si_signext:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_si_signext:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_si_signext:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_si_signext:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_si_signext:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatsisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_si_signext:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatsisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i16 %a to half
ret half %1
}
@@ -764,14 +1607,6 @@ define half @fcvt_h_ui(i16 %a) nounwind {
; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_ui:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: lui a1, 16
-; RV32IDZFH-NEXT: addi a1, a1, -1
-; RV32IDZFH-NEXT: and a0, a0, a1
-; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_ui:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lui a1, 16
@@ -780,6 +1615,14 @@ define half @fcvt_h_ui(i16 %a) nounwind {
; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_ui:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: lui a1, 16
+; RV32IDZFH-NEXT: addi a1, a1, -1
+; RV32IDZFH-NEXT: and a0, a0, a1
+; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_ui:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: lui a1, 16
@@ -787,6 +1630,32 @@ define half @fcvt_h_ui(i16 %a) nounwind {
; RV64IDZFH-NEXT: and a0, a0, a1
; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_ui:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __floatunsisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_ui:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __floatunsisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i16 %a to half
ret half %1
}
@@ -797,20 +1666,40 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_ui_zeroext:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatunsisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_ui_zeroext:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatunsisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i16 %a to half
ret half %1
}
@@ -821,20 +1710,41 @@ define half @fcvt_h_w(i32 %a) nounwind {
; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_w:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_w:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_w:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_w:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_w:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatsisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_w:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: call __floatsisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i32 %a to half
ret half %1
}
@@ -846,23 +1756,45 @@ define half @fcvt_h_w_load(i32* %p) nounwind {
; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_w_load:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: lw a0, 0(a0)
-; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_w_load:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lw a0, 0(a0)
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_w_load:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: lw a0, 0(a0)
+; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_w_load:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: lw a0, 0(a0)
; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_w_load:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 0(a0)
+; RV32I-NEXT: call __floatsisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_w_load:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: call __floatsisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%a = load i32, i32* %p
%1 = sitofp i32 %a to half
ret half %1
@@ -874,20 +1806,41 @@ define half @fcvt_h_wu(i32 %a) nounwind {
; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_wu:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_wu:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_wu:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_wu:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_wu:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatunsisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_wu:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: call __floatunsisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i32 %a to half
ret half %1
}
@@ -899,23 +1852,45 @@ define half @fcvt_h_wu_load(i32* %p) nounwind {
; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_wu_load:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: lw a0, 0(a0)
-; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_wu_load:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lwu a0, 0(a0)
; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_wu_load:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: lw a0, 0(a0)
+; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_wu_load:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: lwu a0, 0(a0)
; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_wu_load:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 0(a0)
+; RV32I-NEXT: call __floatunsisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_wu_load:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: call __floatunsisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%a = load i32, i32* %p
%1 = uitofp i32 %a to half
ret half %1
@@ -931,6 +1906,11 @@ define half @fcvt_h_l(i64 %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
+; RV64IZFH-LABEL: fcvt_h_l:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: fcvt.h.l fa0, a0
+; RV64IZFH-NEXT: ret
+;
; RV32IDZFH-LABEL: fcvt_h_l:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
@@ -940,15 +1920,30 @@ define half @fcvt_h_l(i64 %a) nounwind {
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
-; RV64IZFH-LABEL: fcvt_h_l:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.l fa0, a0
-; RV64IZFH-NEXT: ret
-;
; RV64IDZFH-LABEL: fcvt_h_l:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.h.l fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_l:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatdisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_l:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatdisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = sitofp i64 %a to half
ret half %1
}
@@ -963,6 +1958,11 @@ define half @fcvt_h_lu(i64 %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
+; RV64IZFH-LABEL: fcvt_h_lu:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: fcvt.h.lu fa0, a0
+; RV64IZFH-NEXT: ret
+;
; RV32IDZFH-LABEL: fcvt_h_lu:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
@@ -972,15 +1972,30 @@ define half @fcvt_h_lu(i64 %a) nounwind {
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
-; RV64IZFH-LABEL: fcvt_h_lu:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.lu fa0, a0
-; RV64IZFH-NEXT: ret
-;
; RV64IDZFH-LABEL: fcvt_h_lu:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_lu:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __floatundisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_lu:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __floatundisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = uitofp i64 %a to half
ret half %1
}
@@ -991,20 +2006,38 @@ define half @fcvt_h_s(float %a) nounwind {
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_s:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_s:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_s:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_s:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_s:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_s:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptrunc float %a to half
ret half %1
}
@@ -1015,20 +2048,44 @@ define float @fcvt_s_h(half %a) nounwind {
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_s_h:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_s_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_s_h:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_s_h:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_s_h:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_s_h:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fpext half %a to float
ret float %1
}
@@ -1043,11 +2100,6 @@ define half @fcvt_h_d(double %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_d:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.h.d fa0, fa0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_d:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
@@ -1057,10 +2109,33 @@ define half @fcvt_h_d(double %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_d:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.h.d fa0, fa0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_d:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.h.d fa0, fa0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_d:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __truncdfhf2 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_d:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call __truncdfhf2 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fptrunc double %a to half
ret half %1
}
@@ -1076,11 +2151,6 @@ define double @fcvt_d_h(half %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_d_h:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.d.h fa0, fa0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_d_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
@@ -1091,10 +2161,43 @@ define double @fcvt_d_h(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_d_h:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.d.h fa0, fa0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_d_h:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.d.h fa0, fa0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_d_h:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call __extendsfdf2 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_d_h:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: srli a0, a0, 32
+; RV64I-NEXT: call __extendsfdf2 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = fpext half %a to double
ret double %1
}
@@ -1105,20 +2208,28 @@ define half @bitcast_h_i16(i16 %a) nounwind {
; RV32IZFH-NEXT: fmv.h.x fa0, a0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: bitcast_h_i16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmv.h.x fa0, a0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: bitcast_h_i16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x fa0, a0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: bitcast_h_i16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fmv.h.x fa0, a0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: bitcast_h_i16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fmv.h.x fa0, a0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: bitcast_h_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: bitcast_h_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
%1 = bitcast i16 %a to half
ret half %1
}
@@ -1129,20 +2240,28 @@ define i16 @bitcast_i16_h(half %a) nounwind {
; RV32IZFH-NEXT: fmv.x.h a0, fa0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: bitcast_i16_h:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmv.x.h a0, fa0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: bitcast_i16_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.x.h a0, fa0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: bitcast_i16_h:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fmv.x.h a0, fa0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: bitcast_i16_h:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fmv.x.h a0, fa0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: bitcast_i16_h:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: bitcast_i16_h:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
%1 = bitcast half %a to i16
ret i16 %1
}
@@ -1156,13 +2275,6 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
; RV32IZFH-NEXT: fsh ft0, 0(a1)
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi a0, a0, 1
-; RV32IDZFH-NEXT: fcvt.h.w ft0, a0
-; RV32IDZFH-NEXT: fsh ft0, 0(a1)
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_w_demanded_bits:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addiw a0, a0, 1
@@ -1170,12 +2282,65 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
; RV64IZFH-NEXT: fsh ft0, 0(a1)
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi a0, a0, 1
+; RV32IDZFH-NEXT: fcvt.h.w ft0, a0
+; RV32IDZFH-NEXT: fsh ft0, 0(a1)
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addiw a0, a0, 1
; RV64IDZFH-NEXT: fcvt.h.w ft0, a0
; RV64IDZFH-NEXT: fsh ft0, 0(a1)
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_w_demanded_bits:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: addi s1, a0, 1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __floatsisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: sh a0, 0(s0)
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_w_demanded_bits:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
+; RV64I-NEXT: .cfi_offset s1, -24
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: addiw s1, a0, 1
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __floatsisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: sh a0, 0(s0)
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%3 = add i32 %0, 1
%4 = sitofp i32 %3 to half
store half %4, half* %1, align 2
@@ -1191,13 +2356,6 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {
; RV32IZFH-NEXT: fsh ft0, 0(a1)
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi a0, a0, 1
-; RV32IDZFH-NEXT: fcvt.h.wu ft0, a0
-; RV32IDZFH-NEXT: fsh ft0, 0(a1)
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addiw a0, a0, 1
@@ -1205,12 +2363,65 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {
; RV64IZFH-NEXT: fsh ft0, 0(a1)
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi a0, a0, 1
+; RV32IDZFH-NEXT: fcvt.h.wu ft0, a0
+; RV32IDZFH-NEXT: fsh ft0, 0(a1)
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addiw a0, a0, 1
; RV64IDZFH-NEXT: fcvt.h.wu ft0, a0
; RV64IDZFH-NEXT: fsh ft0, 0(a1)
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fcvt_h_wu_demanded_bits:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: addi s1, a0, 1
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call __floatunsisf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: sh a0, 0(s0)
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcvt_h_wu_demanded_bits:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
+; RV64I-NEXT: .cfi_offset s1, -24
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: addiw s1, a0, 1
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call __floatunsisf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: sh a0, 0(s0)
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%3 = add i32 %0, 1
%4 = uitofp i32 %3 to half
store half %4, half* %1, align 2
diff --git a/llvm/test/CodeGen/RISCV/half-fcmp.ll b/llvm/test/CodeGen/RISCV/half-fcmp.ll
index a8a98fae4d60..8fb5c06cd258 100644
--- a/llvm/test/CodeGen/RISCV/half-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-fcmp.ll
@@ -3,6 +3,10 @@
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
+; RUN: < %s | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
+; RUN: < %s | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_false:
@@ -14,6 +18,16 @@ define i32 @fcmp_false(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: mv a0, zero
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_false:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a0, zero
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_false:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a0, zero
+; RV64I-NEXT: ret
%1 = fcmp false half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -29,6 +43,20 @@ define i32 @fcmp_oeq(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_oeq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a1
+; RV32I-NEXT: fmv.h.x ft1, a0
+; RV32I-NEXT: feq.h a0, ft1, ft0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_oeq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a1
+; RV64I-NEXT: fmv.h.x ft1, a0
+; RV64I-NEXT: feq.h a0, ft1, ft0
+; RV64I-NEXT: ret
%1 = fcmp oeq half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -44,6 +72,20 @@ define i32 @fcmp_ogt(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ogt:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a0
+; RV32I-NEXT: fmv.h.x ft1, a1
+; RV32I-NEXT: flt.h a0, ft1, ft0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ogt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a0
+; RV64I-NEXT: fmv.h.x ft1, a1
+; RV64I-NEXT: flt.h a0, ft1, ft0
+; RV64I-NEXT: ret
%1 = fcmp ogt half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -59,6 +101,20 @@ define i32 @fcmp_oge(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_oge:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a0
+; RV32I-NEXT: fmv.h.x ft1, a1
+; RV32I-NEXT: fle.h a0, ft1, ft0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_oge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a0
+; RV64I-NEXT: fmv.h.x ft1, a1
+; RV64I-NEXT: fle.h a0, ft1, ft0
+; RV64I-NEXT: ret
%1 = fcmp oge half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -74,6 +130,20 @@ define i32 @fcmp_olt(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_olt:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a1
+; RV32I-NEXT: fmv.h.x ft1, a0
+; RV32I-NEXT: flt.h a0, ft1, ft0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_olt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a1
+; RV64I-NEXT: fmv.h.x ft1, a0
+; RV64I-NEXT: flt.h a0, ft1, ft0
+; RV64I-NEXT: ret
%1 = fcmp olt half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -89,6 +159,20 @@ define i32 @fcmp_ole(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ole:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a1
+; RV32I-NEXT: fmv.h.x ft1, a0
+; RV32I-NEXT: fle.h a0, ft1, ft0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ole:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a1
+; RV64I-NEXT: fmv.h.x ft1, a0
+; RV64I-NEXT: fle.h a0, ft1, ft0
+; RV64I-NEXT: ret
%1 = fcmp ole half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -108,6 +192,24 @@ define i32 @fcmp_one(half %a, half %b) nounwind {
; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_one:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a1
+; RV32I-NEXT: fmv.h.x ft1, a0
+; RV32I-NEXT: flt.h a0, ft1, ft0
+; RV32I-NEXT: flt.h a1, ft0, ft1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_one:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a1
+; RV64I-NEXT: fmv.h.x ft1, a0
+; RV64I-NEXT: flt.h a0, ft1, ft0
+; RV64I-NEXT: flt.h a1, ft0, ft1
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: ret
%1 = fcmp one half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -127,6 +229,24 @@ define i32 @fcmp_ord(half %a, half %b) nounwind {
; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ord:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a0
+; RV32I-NEXT: fmv.h.x ft1, a1
+; RV32I-NEXT: feq.h a0, ft1, ft1
+; RV32I-NEXT: feq.h a1, ft0, ft0
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ord:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a0
+; RV64I-NEXT: fmv.h.x ft1, a1
+; RV64I-NEXT: feq.h a0, ft1, ft1
+; RV64I-NEXT: feq.h a1, ft0, ft0
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: ret
%1 = fcmp ord half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -148,6 +268,26 @@ define i32 @fcmp_ueq(half %a, half %b) nounwind {
; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ueq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a1
+; RV32I-NEXT: fmv.h.x ft1, a0
+; RV32I-NEXT: flt.h a0, ft1, ft0
+; RV32I-NEXT: flt.h a1, ft0, ft1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ueq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a1
+; RV64I-NEXT: fmv.h.x ft1, a0
+; RV64I-NEXT: flt.h a0, ft1, ft0
+; RV64I-NEXT: flt.h a1, ft0, ft1
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
%1 = fcmp ueq half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -165,6 +305,22 @@ define i32 @fcmp_ugt(half %a, half %b) nounwind {
; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ugt:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a1
+; RV32I-NEXT: fmv.h.x ft1, a0
+; RV32I-NEXT: fle.h a0, ft1, ft0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ugt:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a1
+; RV64I-NEXT: fmv.h.x ft1, a0
+; RV64I-NEXT: fle.h a0, ft1, ft0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
%1 = fcmp ugt half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -182,6 +338,22 @@ define i32 @fcmp_uge(half %a, half %b) nounwind {
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_uge:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a1
+; RV32I-NEXT: fmv.h.x ft1, a0
+; RV32I-NEXT: flt.h a0, ft1, ft0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_uge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a1
+; RV64I-NEXT: fmv.h.x ft1, a0
+; RV64I-NEXT: flt.h a0, ft1, ft0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
%1 = fcmp uge half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -199,6 +371,22 @@ define i32 @fcmp_ult(half %a, half %b) nounwind {
; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ult:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a0
+; RV32I-NEXT: fmv.h.x ft1, a1
+; RV32I-NEXT: fle.h a0, ft1, ft0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ult:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a0
+; RV64I-NEXT: fmv.h.x ft1, a1
+; RV64I-NEXT: fle.h a0, ft1, ft0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
%1 = fcmp ult half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -216,6 +404,22 @@ define i32 @fcmp_ule(half %a, half %b) nounwind {
; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_ule:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a0
+; RV32I-NEXT: fmv.h.x ft1, a1
+; RV32I-NEXT: flt.h a0, ft1, ft0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_ule:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a0
+; RV64I-NEXT: fmv.h.x ft1, a1
+; RV64I-NEXT: flt.h a0, ft1, ft0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
%1 = fcmp ule half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -233,6 +437,22 @@ define i32 @fcmp_une(half %a, half %b) nounwind {
; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_une:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a1
+; RV32I-NEXT: fmv.h.x ft1, a0
+; RV32I-NEXT: feq.h a0, ft1, ft0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_une:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a1
+; RV64I-NEXT: fmv.h.x ft1, a0
+; RV64I-NEXT: feq.h a0, ft1, ft0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
%1 = fcmp une half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -254,6 +474,26 @@ define i32 @fcmp_uno(half %a, half %b) nounwind {
; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_uno:
+; RV32I: # %bb.0:
+; RV32I-NEXT: fmv.h.x ft0, a0
+; RV32I-NEXT: fmv.h.x ft1, a1
+; RV32I-NEXT: feq.h a0, ft1, ft1
+; RV32I-NEXT: feq.h a1, ft0, ft0
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_uno:
+; RV64I: # %bb.0:
+; RV64I-NEXT: fmv.h.x ft0, a0
+; RV64I-NEXT: fmv.h.x ft1, a1
+; RV64I-NEXT: feq.h a0, ft1, ft1
+; RV64I-NEXT: feq.h a1, ft0, ft0
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: ret
%1 = fcmp uno half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -269,6 +509,16 @@ define i32 @fcmp_true(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi a0, zero, 1
; RV64IZFH-NEXT: ret
+;
+; RV32I-LABEL: fcmp_true:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a0, zero, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fcmp_true:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a0, zero, 1
+; RV64I-NEXT: ret
%1 = fcmp true half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
index 89d553f1b4f2..13e6ea9c8470 100644
--- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
@@ -2,15 +2,21 @@
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+experimental-zfh \
; RUN: -verify-machineinstrs -target-abi ilp32f | \
; RUN: FileCheck -check-prefix=RV32IZFH %s
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
-; RUN: -mattr=+experimental-zfh -verify-machineinstrs -target-abi ilp32d | \
-; RUN: FileCheck -check-prefix=RV32IDZFH %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+experimental-zfh \
; RUN: -verify-machineinstrs -target-abi lp64f | \
; RUN: FileCheck -check-prefix=RV64IZFH %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
+; RUN: -mattr=+experimental-zfh -verify-machineinstrs -target-abi ilp32d | \
+; RUN: FileCheck -check-prefix=RV32IDZFH %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
; RUN: -mattr=+experimental-zfh -verify-machineinstrs -target-abi lp64d | \
; RUN: FileCheck -check-prefix=RV64IDZFH %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
+; RUN: -verify-machineinstrs | \
+; RUN: FileCheck -check-prefix=RV32I %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
+; RUN: -verify-machineinstrs | \
+; RUN: FileCheck -check-prefix=RV64I %s
declare half @llvm.sqrt.f16(half)
@@ -20,20 +26,48 @@ define half @sqrt_f16(half %a) nounwind {
; RV32IZFH-NEXT: fsqrt.h fa0, fa0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: sqrt_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fsqrt.h fa0, fa0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: sqrt_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fsqrt.h fa0, fa0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: sqrt_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fsqrt.h fa0, fa0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: sqrt_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fsqrt.h fa0, fa0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: sqrt_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call sqrtf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: sqrt_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call sqrtf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call half @llvm.sqrt.f16(half %a)
ret half %1
}
@@ -46,20 +80,86 @@ define half @fma_f16(half %a, half %b, half %c) nounwind {
; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fma_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fma_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fma_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fma_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fma_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a2
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: and a0, s1, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a0, s3
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call fmaf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fma_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: and a0, s1, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: mv a0, s3
+; RV64I-NEXT: mv a1, s1
+; RV64I-NEXT: call fmaf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%1 = call half @llvm.fma.f16(half %a, half %b, half %c)
ret half %1
}
@@ -72,20 +172,96 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fmuladd_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fmuladd_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fmuladd_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fmuladd_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fmuladd_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a2
+; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s1, a1, -1
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s3, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call __mulsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: and a0, s2, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: and a0, s0, s1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: call __addsf3 at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fmuladd_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a2
+; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s1, a1, -1
+; RV64I-NEXT: and a0, a0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s3, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __mulsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: and a0, s2, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: and a0, s0, s1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, s2
+; RV64I-NEXT: call __addsf3 at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
%1 = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
ret half %1
}
@@ -98,20 +274,34 @@ define half @fabs_f16(half %a) nounwind {
; RV32IZFH-NEXT: fabs.h fa0, fa0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fabs_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fabs.h fa0, fa0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: fabs_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fabs.h fa0, fa0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: fabs_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fabs.h fa0, fa0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: fabs_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fabs.h fa0, fa0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: fabs_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 8
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fabs_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 8
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
%1 = call half @llvm.fabs.f16(half %a)
ret half %1
}
@@ -124,20 +314,72 @@ define half @minnum_f16(half %a, half %b) nounwind {
; RV32IZFH-NEXT: fmin.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: minnum_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmin.h fa0, fa0, fa1
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: minnum_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmin.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: minnum_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fmin.h fa0, fa0, fa1
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: minnum_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fmin.h fa0, fa0, fa1
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: minnum_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call fminf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: minnum_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call fminf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = call half @llvm.minnum.f16(half %a, half %b)
ret half %1
}
@@ -150,20 +392,72 @@ define half @maxnum_f16(half %a, half %b) nounwind {
; RV32IZFH-NEXT: fmax.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: maxnum_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmax.h fa0, fa0, fa1
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: maxnum_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmax.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: maxnum_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fmax.h fa0, fa0, fa1
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: maxnum_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fmax.h fa0, fa0, fa1
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: maxnum_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s0, a1, -1
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s2, s0
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call fmaxf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: maxnum_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s2, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s0, a1, -1
+; RV64I-NEXT: and a0, a0, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s2, s0
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call fmaxf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%1 = call half @llvm.maxnum.f16(half %a, half %b)
ret half %1
}
@@ -176,20 +470,40 @@ define half @copysign_f16(half %a, half %b) nounwind {
; RV32IZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: copysign_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fsgnj.h fa0, fa0, fa1
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: copysign_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: copysign_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fsgnj.h fa0, fa0, fa1
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: copysign_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: copysign_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 1048568
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: lui a2, 8
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: copysign_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a2, 1048568
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: lui a2, 8
+; RV64I-NEXT: addiw a2, a2, -1
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
%1 = call half @llvm.copysign.f16(half %a, half %b)
ret half %1
}
@@ -208,17 +522,6 @@ define half @floor_f16(half %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: floor_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call floorf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: floor_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
@@ -230,6 +533,17 @@ define half @floor_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: floor_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi sp, sp, -16
+; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: call floorf at plt
+; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: floor_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
@@ -240,6 +554,34 @@ define half @floor_f16(half %a) nounwind {
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: floor_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call floorf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: floor_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call floorf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call half @llvm.floor.f16(half %a)
ret half %1
}
@@ -258,17 +600,6 @@ define half @ceil_f16(half %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: ceil_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call ceilf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: ceil_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
@@ -280,6 +611,17 @@ define half @ceil_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: ceil_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi sp, sp, -16
+; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: call ceilf at plt
+; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: ceil_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
@@ -290,6 +632,34 @@ define half @ceil_f16(half %a) nounwind {
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: ceil_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call ceilf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ceil_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call ceilf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call half @llvm.ceil.f16(half %a)
ret half %1
}
@@ -308,17 +678,6 @@ define half @trunc_f16(half %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: trunc_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call truncf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: trunc_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
@@ -330,6 +689,17 @@ define half @trunc_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: trunc_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi sp, sp, -16
+; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: call truncf at plt
+; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: trunc_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
@@ -340,6 +710,34 @@ define half @trunc_f16(half %a) nounwind {
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: trunc_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call truncf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: trunc_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call truncf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call half @llvm.trunc.f16(half %a)
ret half %1
}
@@ -358,17 +756,6 @@ define half @rint_f16(half %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: rint_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call rintf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: rint_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
@@ -380,6 +767,17 @@ define half @rint_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: rint_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi sp, sp, -16
+; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: call rintf at plt
+; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: rint_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
@@ -390,6 +788,34 @@ define half @rint_f16(half %a) nounwind {
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: rint_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call rintf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: rint_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call rintf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call half @llvm.rint.f16(half %a)
ret half %1
}
@@ -408,17 +834,6 @@ define half @nearbyint_f16(half %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: nearbyint_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call nearbyintf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: nearbyint_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
@@ -430,6 +845,17 @@ define half @nearbyint_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: nearbyint_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi sp, sp, -16
+; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: call nearbyintf at plt
+; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: nearbyint_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
@@ -440,6 +866,34 @@ define half @nearbyint_f16(half %a) nounwind {
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: nearbyint_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call nearbyintf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: nearbyint_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call nearbyintf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call half @llvm.nearbyint.f16(half %a)
ret half %1
}
@@ -458,17 +912,6 @@ define half @round_f16(half %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: round_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call roundf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: round_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
@@ -480,6 +923,17 @@ define half @round_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: round_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi sp, sp, -16
+; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: call roundf at plt
+; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: round_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
@@ -490,6 +944,34 @@ define half @round_f16(half %a) nounwind {
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: round_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call roundf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: round_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call roundf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call half @llvm.round.f16(half %a)
ret half %1
}
@@ -508,17 +990,6 @@ define half @roundeven_f16(half %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: roundeven_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call roundevenf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: roundeven_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
@@ -530,6 +1001,17 @@ define half @roundeven_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: roundeven_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi sp, sp, -16
+; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: call roundevenf at plt
+; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: roundeven_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
@@ -540,6 +1022,34 @@ define half @roundeven_f16(half %a) nounwind {
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: roundeven_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: call __gnu_h2f_ieee at plt
+; RV32I-NEXT: call roundevenf at plt
+; RV32I-NEXT: call __gnu_f2h_ieee at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: roundeven_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: call __gnu_h2f_ieee at plt
+; RV64I-NEXT: call roundevenf at plt
+; RV64I-NEXT: call __gnu_f2h_ieee at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call half @llvm.roundeven.f16(half %a)
ret half %1
}
@@ -552,20 +1062,38 @@ define iXLen @lrint_f16(float %a) nounwind {
; RV32IZFH-NEXT: fcvt.w.s a0, fa0
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: lrint_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.w.s a0, fa0
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: lrint_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.l.s a0, fa0
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: lrint_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.w.s a0, fa0
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: lrint_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.s a0, fa0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: lrint_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call lrintf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: lrint_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call lrintf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call iXLen @llvm.lrint.iXLen.f16(float %a)
ret iXLen %1
}
@@ -578,20 +1106,38 @@ define iXLen @lround_f16(float %a) nounwind {
; RV32IZFH-NEXT: fcvt.w.s a0, fa0, rmm
; RV32IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: lround_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.w.s a0, fa0, rmm
-; RV32IDZFH-NEXT: ret
-;
; RV64IZFH-LABEL: lround_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.l.s a0, fa0, rmm
; RV64IZFH-NEXT: ret
;
+; RV32IDZFH-LABEL: lround_f16:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: fcvt.w.s a0, fa0, rmm
+; RV32IDZFH-NEXT: ret
+;
; RV64IDZFH-LABEL: lround_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.s a0, fa0, rmm
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: lround_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call lroundf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: lround_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call lroundf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call iXLen @llvm.lround.iXLen.f16(float %a)
ret iXLen %1
}
@@ -608,6 +1154,11 @@ define i64 @llrint_f16(float %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
+; RV64IZFH-LABEL: llrint_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: fcvt.l.s a0, fa0
+; RV64IZFH-NEXT: ret
+;
; RV32IDZFH-LABEL: llrint_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
@@ -617,15 +1168,28 @@ define i64 @llrint_f16(float %a) nounwind {
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
-; RV64IZFH-LABEL: llrint_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.l.s a0, fa0
-; RV64IZFH-NEXT: ret
-;
; RV64IDZFH-LABEL: llrint_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.s a0, fa0
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: llrint_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call llrintf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: llrint_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call llrintf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call i64 @llvm.llrint.i64.f16(float %a)
ret i64 %1
}
@@ -642,6 +1206,11 @@ define i64 @llround_f16(float %a) nounwind {
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
+; RV64IZFH-LABEL: llround_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: fcvt.l.s a0, fa0, rmm
+; RV64IZFH-NEXT: ret
+;
; RV32IDZFH-LABEL: llround_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
@@ -651,15 +1220,28 @@ define i64 @llround_f16(float %a) nounwind {
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
-; RV64IZFH-LABEL: llround_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.l.s a0, fa0, rmm
-; RV64IZFH-NEXT: ret
-;
; RV64IDZFH-LABEL: llround_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.s a0, fa0, rmm
; RV64IDZFH-NEXT: ret
+;
+; RV32I-LABEL: llround_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call llroundf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: llround_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call llroundf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%1 = call i64 @llvm.llround.i64.f16(float %a)
ret i64 %1
}
diff --git a/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll b/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
index 0298c21359f3..70a4c1726ca3 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
@@ -7,54 +7,6 @@
; The test cases check that we use the si versions of the conversions from
; double.
-define i32 @fp64_to_ui32(double %a) nounwind {
-; RV64I-LABEL: fp64_to_ui32:
-; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __fixunsdfsi at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
-;
-; RV64IF-LABEL: fp64_to_ui32:
-; RV64IF: # %bb.0: # %entry
-; RV64IF-NEXT: addi sp, sp, -16
-; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-NEXT: call __fixunsdfsi at plt
-; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IF-NEXT: addi sp, sp, 16
-; RV64IF-NEXT: ret
-entry:
- %conv = fptoui double %a to i32
- ret i32 %conv
-}
-
-define i32 @fp64_to_si32(double %a) nounwind {
-; RV64I-LABEL: fp64_to_si32:
-; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __fixdfsi at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
-;
-; RV64IF-LABEL: fp64_to_si32:
-; RV64IF: # %bb.0: # %entry
-; RV64IF-NEXT: addi sp, sp, -16
-; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-NEXT: call __fixdfsi at plt
-; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IF-NEXT: addi sp, sp, 16
-; RV64IF-NEXT: ret
-entry:
- %conv = fptosi double %a to i32
- ret i32 %conv
-}
-
-
-
declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
@@ -81,8 +33,8 @@ entry:
ret i32 %conv
}
-define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
-; RV64I-LABEL: struct_fp64_to_si32:
+define i32 @strict_fp64_to_si32(double %a) nounwind strictfp {
+; RV64I-LABEL: strict_fp64_to_si32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
@@ -91,7 +43,7 @@ define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IF-LABEL: struct_fp64_to_si32:
+; RV64IF-LABEL: strict_fp64_to_si32:
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
diff --git a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
index 9aa17ef1d8da..b7e112bbb7b5 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
@@ -2,736 +2,8 @@
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
-; The test cases check that the single float arguments won't be extended
-; when passing to softfloat functions.
-; RISCV backend using shouldExtendTypeInLibCall target hook to suppress
-; the extension generation.
-
-define float @fadd_s(float %a, float %b) nounwind {
-; RV64I-LABEL: fadd_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __addsf3 at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fadd float %a, %b
- ret float %1
-}
-
-define float @fsub_s(float %a, float %b) nounwind {
-; RV64I-LABEL: fsub_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __subsf3 at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fsub float %a, %b
- ret float %1
-}
-
-define float @fmul_s(float %a, float %b) nounwind {
-; RV64I-LABEL: fmul_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __mulsf3 at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fmul float %a, %b
- ret float %1
-}
-
-define float @fdiv_s(float %a, float %b) nounwind {
-; RV64I-LABEL: fdiv_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __divsf3 at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fdiv float %a, %b
- ret float %1
-}
-
-define i32 @feq_s(float %a, float %b) nounwind {
-; RV64I-LABEL: feq_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __eqsf2 at plt
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fcmp oeq float %a, %b
- %2 = zext i1 %1 to i32
- ret i32 %2
-}
-
-define i32 @flt_s(float %a, float %b) nounwind {
-; RV64I-LABEL: flt_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __ltsf2 at plt
-; RV64I-NEXT: slti a0, a0, 0
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fcmp olt float %a, %b
- %2 = zext i1 %1 to i32
- ret i32 %2
-}
-
-define i32 @fle_s(float %a, float %b) nounwind {
-; RV64I-LABEL: fle_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __lesf2 at plt
-; RV64I-NEXT: slti a0, a0, 1
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fcmp ole float %a, %b
- %2 = zext i1 %1 to i32
- ret i32 %2
-}
-
-define i32 @fcmp_ogt(float %a, float %b) nounwind {
-; RV64I-LABEL: fcmp_ogt:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __gtsf2 at plt
-; RV64I-NEXT: sgtz a0, a0
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fcmp ogt float %a, %b
- %2 = zext i1 %1 to i32
- ret i32 %2
-}
-
-define i32 @fcmp_oge(float %a, float %b) nounwind {
-; RV64I-LABEL: fcmp_oge:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __gesf2 at plt
-; RV64I-NEXT: addi a1, zero, -1
-; RV64I-NEXT: slt a0, a1, a0
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fcmp oge float %a, %b
- %2 = zext i1 %1 to i32
- ret i32 %2
-}
-
-define i32 @fcmp_ord(float %a, float %b) nounwind {
-; RV64I-LABEL: fcmp_ord:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __unordsf2 at plt
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fcmp ord float %a, %b
- %2 = zext i1 %1 to i32
- ret i32 %2
-}
-
-define i32 @fcmp_une(float %a, float %b) nounwind {
-; RV64I-LABEL: fcmp_une:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __nesf2 at plt
-; RV64I-NEXT: snez a0, a0
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fcmp une float %a, %b
- %2 = zext i1 %1 to i32
- ret i32 %2
-}
-
-define i32 @fcvt_w_s(float %a) nounwind {
-; RV64I-LABEL: fcvt_w_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __fixsfsi at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fptosi float %a to i32
- ret i32 %1
-}
-
-define i32 @fcvt_wu_s(float %a) nounwind {
-; RV64I-LABEL: fcvt_wu_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __fixunssfsi at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fptoui float %a to i32
- ret i32 %1
-}
-
-define float @fcvt_s_w(i32 %a) nounwind {
-; RV64I-LABEL: fcvt_s_w:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: call __floatsisf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = sitofp i32 %a to float
- ret float %1
-}
-
-define float @fcvt_s_wu(i32 %a) nounwind {
-; RV64I-LABEL: fcvt_s_wu:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: call __floatunsisf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = uitofp i32 %a to float
- ret float %1
-}
-
-define i64 @fcvt_l_s(float %a) nounwind {
-; RV64I-LABEL: fcvt_l_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __fixsfdi at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fptosi float %a to i64
- ret i64 %1
-}
-
-define i64 @fcvt_lu_s(float %a) nounwind {
-; RV64I-LABEL: fcvt_lu_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __fixunssfdi at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = fptoui float %a to i64
- ret i64 %1
-}
-
-define float @fcvt_s_l(i64 %a) nounwind {
-; RV64I-LABEL: fcvt_s_l:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __floatdisf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = sitofp i64 %a to float
- ret float %1
-}
-
-define float @fcvt_s_lu(i64 %a) nounwind {
-; RV64I-LABEL: fcvt_s_lu:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __floatundisf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = uitofp i64 %a to float
- ret float %1
-}
-
-declare float @llvm.sqrt.f32(float)
-
-define float @fsqrt_s(float %a) nounwind {
-; RV64I-LABEL: fsqrt_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call sqrtf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.sqrt.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.copysign.f32(float, float)
-
-define float @fsgnj_s(float %a, float %b) nounwind {
-; RV64I-LABEL: fsgnj_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: lui a2, 524288
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: addiw a2, a2, -1
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: ret
- %1 = call float @llvm.copysign.f32(float %a, float %b)
- ret float %1
-}
-
-declare float @llvm.minnum.f32(float, float)
-
-define float @fmin_s(float %a, float %b) nounwind {
-; RV64I-LABEL: fmin_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call fminf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.minnum.f32(float %a, float %b)
- ret float %1
-}
-
-declare float @llvm.maxnum.f32(float, float)
-
-define float @fmax_s(float %a, float %b) nounwind {
-; RV64I-LABEL: fmax_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call fmaxf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.maxnum.f32(float %a, float %b)
- ret float %1
-}
-
-
-declare float @llvm.fma.f32(float, float, float)
-
-define float @fmadd_s(float %a, float %b, float %c) nounwind {
-; RV64I-LABEL: fmadd_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call fmaf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
- ret float %1
-}
-
-define float @fmsub_s(float %a, float %b, float %c) nounwind {
-; RV64I-LABEL: fmsub_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -32
-; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: mv a0, a2
-; RV64I-NEXT: mv a1, zero
-; RV64I-NEXT: call __addsf3 at plt
-; RV64I-NEXT: lui a1, 524288
-; RV64I-NEXT: xor a2, a0, a1
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s0
-; RV64I-NEXT: call fmaf at plt
-; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 32
-; RV64I-NEXT: ret
- %c_ = fadd float 0.0, %c ; avoid negation using xor
- %negc = fsub float -0.0, %c_
- %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
- ret float %1
-}
-
-define float @fnmadd_s(float %a, float %b, float %c) nounwind {
-; RV64I-LABEL: fnmadd_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -32
-; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a2
-; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv a1, zero
-; RV64I-NEXT: call __addsf3 at plt
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, zero
-; RV64I-NEXT: call __addsf3 at plt
-; RV64I-NEXT: lui a2, 524288
-; RV64I-NEXT: xor a1, s1, a2
-; RV64I-NEXT: xor a2, a0, a2
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: mv a1, s2
-; RV64I-NEXT: call fmaf at plt
-; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 32
-; RV64I-NEXT: ret
- %a_ = fadd float 0.0, %a
- %c_ = fadd float 0.0, %c
- %nega = fsub float -0.0, %a_
- %negc = fsub float -0.0, %c_
- %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
- ret float %1
-}
-
-define float @fnmsub_s(float %a, float %b, float %c) nounwind {
-; RV64I-LABEL: fnmsub_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -32
-; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a2
-; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: mv a1, zero
-; RV64I-NEXT: call __addsf3 at plt
-; RV64I-NEXT: lui a1, 524288
-; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: mv a1, s1
-; RV64I-NEXT: mv a2, s0
-; RV64I-NEXT: call fmaf at plt
-; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 32
-; RV64I-NEXT: ret
- %a_ = fadd float 0.0, %a
- %nega = fsub float -0.0, %a_
- %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
- ret float %1
-}
-
-declare float @llvm.ceil.f32(float)
-
-define float @fceil_s(float %a) nounwind {
-; RV64I-LABEL: fceil_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call ceilf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.ceil.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.cos.f32(float)
-
-define float @fcos_s(float %a) nounwind {
-; RV64I-LABEL: fcos_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call cosf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.cos.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.sin.f32(float)
-
-define float @fsin_s(float %a) nounwind {
-; RV64I-LABEL: fsin_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call sinf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.sin.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.exp.f32(float)
-
-define float @fexp_s(float %a) nounwind {
-; RV64I-LABEL: fexp_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call expf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.exp.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.exp2.f32(float)
-
-define float @fexp2_s(float %a) nounwind {
-; RV64I-LABEL: fexp2_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call exp2f at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.exp2.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.floor.f32(float)
-
-define float @ffloor_s(float %a) nounwind {
-; RV64I-LABEL: ffloor_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call floorf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.floor.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.log.f32(float)
-
-define float @flog_s(float %a) nounwind {
-; RV64I-LABEL: flog_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call logf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.log.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.log2.f32(float)
-
-define float @flog2_s(float %a) nounwind {
-; RV64I-LABEL: flog2_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call log2f at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.log2.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.log10.f32(float)
-
-define float @flog10_s(float %a) nounwind {
-; RV64I-LABEL: flog10_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call log10f at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.log10.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.nearbyint.f32(float)
-
-define float @fnearbyint_s(float %a) nounwind {
-; RV64I-LABEL: fnearbyint_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call nearbyintf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.nearbyint.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.round.f32(float)
-
-define float @fround_s(float %a) nounwind {
-; RV64I-LABEL: fround_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call roundf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.round.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.roundeven.f32(float)
-
-define float @froundeven_s(float %a) nounwind {
-; RV64I-LABEL: froundeven_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call roundevenf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.roundeven.f32(float %a)
- ret float %1
-}
-
-declare float @llvm.rint.f32(float)
-
-define float @frint_s(float %a) nounwind {
-; RV64I-LABEL: frint_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call rintf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.rint.f32(float %a)
- ret float %1
-}
-
-define float @frem_s(float %a, float %b) nounwind {
-; RV64I-LABEL: frem_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call fmodf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = frem float %a, %b
- ret float %1
-}
-
-declare float @llvm.pow.f32(float %Val, float %power)
-
-define float @fpow_s(float %a, float %b) nounwind {
-; RV64I-LABEL: fpow_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call powf at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.pow.f32(float %a, float %b)
- ret float %1
-}
-
-declare float @llvm.powi.f32.i32(float %Val, i32 %power)
-
-define float @fpowi_s(float %a, i32 %b) nounwind {
-; RV64I-LABEL: fpowi_s:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sext.w a1, a1
-; RV64I-NEXT: call __powisf2 at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %1 = call float @llvm.powi.f32.i32(float %a, i32 %b)
- ret float %1
-}
-
-define double @fp_ext(float %a) nounwind {
-; RV64I-LABEL: fp_ext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __extendsfdf2 at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %conv = fpext float %a to double
- ret double %conv
-}
-
-define float @fp_trunc(double %a) nounwind {
-; RV64I-LABEL: fp_trunc:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __truncdfsf2 at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
- %conv = fptrunc double %a to float
- ret float %conv
-}
-
-define i32 @fp32_to_ui32(float %a) nounwind {
-; RV64I-LABEL: fp32_to_ui32:
-; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __fixunssfsi at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
-entry:
- %conv = fptoui float %a to i32
- ret i32 %conv
-}
-
-define i32 @fp32_to_si32(float %a) nounwind {
-; RV64I-LABEL: fp32_to_si32:
-; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call __fixsfsi at plt
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
-entry:
- %conv = fptosi float %a to i32
- ret i32 %conv
-}
-
-
+; The test cases check that we use the si versions of the conversions from
+; double.
declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
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