[PATCH] D113281: [AArch64][SVE] Generate ASRD instructions for power of 2 signed divides

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12941
+      Subtarget->hasSVE() &&
+      (VT.isScalableVector() || useSVEForFixedLengthVectorVT(VT, true));
+  bool IsFoldableScalar = VT == MVT::i32 || VT == MVT::i64;
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Given this is a dag combine does this need to ensure `VT` is a legal type before it can safely emit an `AArch64ISD` specific node?  `useSVEForFixedLengthVectorVT` has probably got you covered for fixed-length types but you're also handling scalable vector types here.

Just a thought but given the `isIntDivCheap` logic above I'm wondering if it is better to do likewise for vectors when SVE will be used, i.e. just say they're cheap and then have isel rules to lower them to `ASRD`.  I believe this'll mean you'll get free handling for the larger than legal types.

That said, the one thing I'm not sure about is if that makes the handling of `isNegatedPowerOf2` cases more awkward.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113281/new/

https://reviews.llvm.org/D113281