[PATCH] D113603: [x86] fold vector (X > -1) & Y to shift+andn

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 386544.
spatel marked 3 inline comments as done.
spatel edited the summary of this revision.
spatel added a comment.

Patch updated:

1. Spell out "BitWidth" in code comment and patch description for less confusion.
2. Use local SDValue names for matching to avoid swap risk in subsequent folds.
3. Create x86 shift node directly.
4. Rebase after 11522cfcad6b <https://reviews.llvm.org/rG11522cfcad6ba38b0b61a727a711adeef98571c9> / D113426 <https://reviews.llvm.org/D113426> - so all of the results in the "vselect-zero.ll" file are ideal now if I'm seeing it properly.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113603/new/

https://reviews.llvm.org/D113603

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/vector-pcmp.ll
  llvm/test/CodeGen/X86/vselect-zero.ll

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