[llvm] 8e85717 - [RISCV] Fix non-sensical intrinsic names in rv64i-single-softfloat.ll. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-11-11T08:36:34-08:00
New Revision: 8e85717dbf2fc89628a767d256b22694f34f7e07

URL: https://github.com/llvm/llvm-project/commit/8e85717dbf2fc89628a767d256b22694f34f7e07
DIFF: https://github.com/llvm/llvm-project/commit/8e85717dbf2fc89628a767d256b22694f34f7e07.diff

LOG: [RISCV] Fix non-sensical intrinsic names in rv64i-single-softfloat.ll. NFC

Many of these had an extra 'f' at the beginning of their name that
caused them to not be treated as intrinsics.

I'm not sure what fpround was supposed to be so I deleted it.

frem was changed from an intrinsic to an instruction.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D113528

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
index 8527b117910f..9aa17ef1d8da 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
@@ -528,63 +528,63 @@ define float @ffloor_s(float %a) nounwind {
   ret float %1
 }
 
-declare float @llvm.flog.f32(float)
+declare float @llvm.log.f32(float)
 
-define float @fflog_s(float %a) nounwind {
-; RV64I-LABEL: fflog_s:
+define float @flog_s(float %a) nounwind {
+; RV64I-LABEL: flog_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.flog.f32 at plt
+; RV64I-NEXT:    call logf at plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.flog.f32(float %a)
+  %1 = call float @llvm.log.f32(float %a)
   ret float %1
 }
 
-declare float @llvm.flog2.f32(float)
+declare float @llvm.log2.f32(float)
 
-define float @fflog2_s(float %a) nounwind {
-; RV64I-LABEL: fflog2_s:
+define float @flog2_s(float %a) nounwind {
+; RV64I-LABEL: flog2_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.flog2.f32 at plt
+; RV64I-NEXT:    call log2f at plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.flog2.f32(float %a)
+  %1 = call float @llvm.log2.f32(float %a)
   ret float %1
 }
 
-declare float @llvm.flog10.f32(float)
+declare float @llvm.log10.f32(float)
 
-define float @fflog10_s(float %a) nounwind {
-; RV64I-LABEL: fflog10_s:
+define float @flog10_s(float %a) nounwind {
+; RV64I-LABEL: flog10_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.flog10.f32 at plt
+; RV64I-NEXT:    call log10f at plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.flog10.f32(float %a)
+  %1 = call float @llvm.log10.f32(float %a)
   ret float %1
 }
 
-declare float @llvm.fnearbyint.f32(float)
+declare float @llvm.nearbyint.f32(float)
 
 define float @fnearbyint_s(float %a) nounwind {
 ; RV64I-LABEL: fnearbyint_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.fnearbyint.f32 at plt
+; RV64I-NEXT:    call nearbyintf at plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.fnearbyint.f32(float %a)
+  %1 = call float @llvm.nearbyint.f32(float %a)
   ret float %1
 }
 
@@ -618,21 +618,6 @@ define float @froundeven_s(float %a) nounwind {
   ret float %1
 }
 
-declare float @llvm.fpround.f32(float)
-
-define float @fpround_s(float %a) nounwind {
-; RV64I-LABEL: fpround_s:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.fpround.f32 at plt
-; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    ret
-  %1 = call float @llvm.fpround.f32(float %a)
-  ret float %1
-}
-
 declare float @llvm.rint.f32(float)
 
 define float @frint_s(float %a) nounwind {
@@ -648,18 +633,16 @@ define float @frint_s(float %a) nounwind {
   ret float %1
 }
 
-declare float @llvm.rem.f32(float)
-
-define float @frem_s(float %a) nounwind {
+define float @frem_s(float %a, float %b) nounwind {
 ; RV64I-LABEL: frem_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.rem.f32 at plt
+; RV64I-NEXT:    call fmodf at plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.rem.f32(float %a)
+  %1 = frem float %a, %b
   ret float %1
 }