[PATCH] D113475: [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 11 07:36:46 PST 2021
luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.
LGTM now. Thanks!
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Comment at: llvm/include/llvm/Target/Target.td:664-665
+class CompressPat<dag input, dag output, list<Predicate> predicates = []> {
+ dag Input = input;
+ dag Output = output;
+ list<Predicate> Predicates = predicates;
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nit: remove the extraneous spaces. (I know it was already like this in the RISC-V version).
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D113475/new/
https://reviews.llvm.org/D113475
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