[llvm] c969009 - [AMDGPU] Small correction in SITargetLowering::performOrCombine().
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Wed Nov 10 18:07:45 PST 2021
Author: kpyzhov
Date: 2021-11-10T21:07:27-05:00
New Revision: c9690092c8b73791dc49a35824f9cccd386a30b8
URL: https://github.com/llvm/llvm-project/commit/c9690092c8b73791dc49a35824f9cccd386a30b8
DIFF: https://github.com/llvm/llvm-project/commit/c9690092c8b73791dc49a35824f9cccd386a30b8.diff
LOG: [AMDGPU] Small correction in SITargetLowering::performOrCombine().
Differential Revision: https://reviews.llvm.org/D113203
Added:
llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 877b4500364e..519c5b936536 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -9484,7 +9484,8 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,
const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
if (CRHS) {
if (SDValue Split
- = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR, LHS, CRHS))
+ = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR,
+ N->getOperand(0), CRHS))
return Split;
}
diff --git a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
new file mode 100644
index 000000000000..65ffba83df95
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
@@ -0,0 +1,31 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -o - %s | FileCheck %s
+
+; The OR instruction should not be eliminated by the "OR Combine" DAG optimization.
+
+; CHECK-LABEL: _Z11test_kernelPii:
+; CHECK: s_mul_i32
+; CHECK: s_sub_i32
+; CHECK: s_and_b32 [[S1:s[0-9]+]], {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK: s_add_i32 [[S2:s[0-9]+]], {{s[0-9]+}}, [[S1]]
+; CHECK: s_or_b32 {{s[0-9]+}}, [[S2]], 0xc0
+
+define protected amdgpu_kernel void @_Z11test_kernelPii(i32 addrspace(1)* nocapture %Ad.coerce, i32 %s) local_unnamed_addr #5 {
+entry:
+ %rem.lhs.trunc = trunc i32 %s to i16
+ %rem4 = urem i16 %rem.lhs.trunc, 12
+ %rem.zext = zext i16 %rem4 to i32
+ %cmp = icmp eq i32 %s, 3
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ %idxprom = zext i32 %s to i64
+ %arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %Ad.coerce, i64 %idxprom
+ %div = lshr i32 %rem.zext, 3
+ %or = or i32 %rem.zext, 192
+ %add = add nuw nsw i32 %or, %div
+ store i32 %add, i32 addrspace(1)* %arrayidx3, align 4
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
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