[PATCH] D113603: [x86] fold vector (X > -1) & Y to shift+andn

[Sanjay Patel via Phabricator via llvm-commits]

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and (pcmpgt X, -1), Y --> pandn (sra X, BW-1), Y

This avoids the -1 constant vector in favor of an arithmetic shift instruction if it exists (the ISA is still not complete after all these years...).
We catch this pattern late in combining by matching PCMPGT, so it should not interfere with more general folds.

The test diffs are against trunk. This should eliminate lumps in D113426 <https://reviews.llvm.org/D113426> (if we want to see the cumulative results, I can rebase on top of that).


https://reviews.llvm.org/D113603

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/vector-pcmp.ll
  llvm/test/CodeGen/X86/vselect-zero.ll

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