[PATCH] D113426: [DAGCombiner] add fold for vselect based on mask of signbit, part 3

[Sanjay Patel via Phabricator via llvm-commits]

spatel marked an inline comment as done.
spatel added inline comments.


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Comment at: llvm/test/CodeGen/X86/vselect-zero.ll:977
 ; AVX2-NEXT:    vpcmpgtd %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpand %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
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RKSimon wrote:
> Any ideas why AVX2 fails to fold to ANDN(SRA(X,31),Y) ?
Yes - it's actually most of SSE and AVX1/2. We have a fold that turns "not (sra X, BW-1)" into "X > -1", so we need to match that instead.
I have an x86 patch in progress for it and should have that posted soon.

I added more tests with:
51baafd2382283c9


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  https://reviews.llvm.org/D113426/new/

https://reviews.llvm.org/D113426