[llvm] 599f44d - [InstCombine] Add tests for and/or of range checks (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 9 13:06:10 PST 2021
Author: Nikita Popov
Date: 2021-11-09T22:06:02+01:00
New Revision: 599f44d66ca0f9e5bb3d1821ab8d7235d134ef39
URL: https://github.com/llvm/llvm-project/commit/599f44d66ca0f9e5bb3d1821ab8d7235d134ef39
DIFF: https://github.com/llvm/llvm-project/commit/599f44d66ca0f9e5bb3d1821ab8d7235d134ef39.diff
LOG: [InstCombine] Add tests for and/or of range checks (NFC)
Added:
Modified:
llvm/test/Transforms/InstCombine/and-or-icmps.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
index a9c5d2b1c1b81..7fae2b632abcb 100644
--- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll
+++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
@@ -580,9 +580,9 @@ define i1 @PR42691_7_logical(i32 %x) {
define i1 @PR42691_8(i32 %x) {
; CHECK-LABEL: @PR42691_8(
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], -2147483635
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483635
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%c1 = icmp slt i32 %x, 14
%c2 = icmp ne i32 %x, -2147483648
@@ -592,9 +592,9 @@ define i1 @PR42691_8(i32 %x) {
define i1 @PR42691_8_logical(i32 %x) {
; CHECK-LABEL: @PR42691_8_logical(
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], -2147483635
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483635
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%c1 = icmp slt i32 %x, 14
%c2 = icmp ne i32 %x, -2147483648
@@ -604,9 +604,9 @@ define i1 @PR42691_8_logical(i32 %x) {
define i1 @PR42691_9(i32 %x) {
; CHECK-LABEL: @PR42691_9(
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], 2147483633
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -14
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2147483633
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%c1 = icmp sgt i32 %x, 13
%c2 = icmp ne i32 %x, 2147483647
@@ -616,9 +616,9 @@ define i1 @PR42691_9(i32 %x) {
define i1 @PR42691_9_logical(i32 %x) {
; CHECK-LABEL: @PR42691_9_logical(
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], 2147483633
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -14
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2147483633
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%c1 = icmp sgt i32 %x, 13
%c2 = icmp ne i32 %x, 2147483647
@@ -628,9 +628,9 @@ define i1 @PR42691_9_logical(i32 %x) {
define i1 @PR42691_10(i32 %x) {
; CHECK-LABEL: @PR42691_10(
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], -15
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -14
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -15
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%c1 = icmp ugt i32 %x, 13
%c2 = icmp ne i32 %x, 4294967295
@@ -640,9 +640,9 @@ define i1 @PR42691_10(i32 %x) {
define i1 @PR42691_10_logical(i32 %x) {
; CHECK-LABEL: @PR42691_10_logical(
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], -15
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -14
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -15
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%c1 = icmp ugt i32 %x, 13
%c2 = icmp ne i32 %x, 4294967295
@@ -1043,3 +1043,147 @@ define i1 @substitute_constant_or_ne_ule_use2_logical(i8 %x, i8 %y) {
%r = select i1 %c2, i1 true, i1 %c1
ret i1 %r
}
+
+define i1 @or_ranges_overlap(i8 %x) {
+; CHECK-LABEL: @or_ranges_overlap(
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 6
+; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[X]], -10
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i8 [[TMP3]], 11
+; CHECK-NEXT: [[C7:%.*]] = or i1 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C7]]
+;
+ %c1 = icmp uge i8 %x, 5
+ %c2 = icmp ule i8 %x, 10
+ %c3 = and i1 %c1, %c2
+ %c4 = icmp uge i8 %x, 10
+ %c5 = icmp ule i8 %x, 20
+ %c6 = and i1 %c4, %c5
+ %c7 = or i1 %c3, %c6
+ ret i1 %c7
+}
+
+define i1 @or_ranges_adjacent(i8 %x) {
+; CHECK-LABEL: @or_ranges_adjacent(
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 6
+; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[X]], -11
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i8 [[TMP3]], 10
+; CHECK-NEXT: [[C7:%.*]] = or i1 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C7]]
+;
+ %c1 = icmp uge i8 %x, 5
+ %c2 = icmp ule i8 %x, 10
+ %c3 = and i1 %c1, %c2
+ %c4 = icmp uge i8 %x, 11
+ %c5 = icmp ule i8 %x, 20
+ %c6 = and i1 %c4, %c5
+ %c7 = or i1 %c3, %c6
+ ret i1 %c7
+}
+
+define i1 @or_ranges_separated(i8 %x) {
+; CHECK-LABEL: @or_ranges_separated(
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 6
+; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[X]], -12
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i8 [[TMP3]], 9
+; CHECK-NEXT: [[C7:%.*]] = or i1 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C7]]
+;
+ %c1 = icmp uge i8 %x, 5
+ %c2 = icmp ule i8 %x, 10
+ %c3 = and i1 %c1, %c2
+ %c4 = icmp uge i8 %x, 12
+ %c5 = icmp ule i8 %x, 20
+ %c6 = and i1 %c4, %c5
+ %c7 = or i1 %c3, %c6
+ ret i1 %c7
+}
+
+define i1 @or_ranges_single_elem_right(i8 %x) {
+; CHECK-LABEL: @or_ranges_single_elem_right(
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 7
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %c1 = icmp uge i8 %x, 5
+ %c2 = icmp ule i8 %x, 10
+ %c3 = and i1 %c1, %c2
+ %c4 = icmp eq i8 %x, 11
+ %c6 = or i1 %c3, %c4
+ ret i1 %c6
+}
+
+define i1 @or_ranges_single_elem_left(i8 %x) {
+; CHECK-LABEL: @or_ranges_single_elem_left(
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 6
+; CHECK-NEXT: [[C4:%.*]] = icmp eq i8 [[X]], 4
+; CHECK-NEXT: [[C6:%.*]] = or i1 [[TMP2]], [[C4]]
+; CHECK-NEXT: ret i1 [[C6]]
+;
+ %c1 = icmp uge i8 %x, 5
+ %c2 = icmp ule i8 %x, 10
+ %c3 = and i1 %c1, %c2
+ %c4 = icmp eq i8 %x, 4
+ %c6 = or i1 %c3, %c4
+ ret i1 %c6
+}
+
+define i1 @and_ranges_overlap(i8 %x) {
+; CHECK-LABEL: @and_ranges_overlap(
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 6
+; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[X]], -7
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i8 [[TMP3]], 14
+; CHECK-NEXT: [[C7:%.*]] = and i1 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C7]]
+;
+ %c1 = icmp uge i8 %x, 5
+ %c2 = icmp ule i8 %x, 10
+ %c3 = and i1 %c1, %c2
+ %c4 = icmp uge i8 %x, 7
+ %c5 = icmp ule i8 %x, 20
+ %c6 = and i1 %c4, %c5
+ %c7 = and i1 %c3, %c6
+ ret i1 %c7
+}
+
+define i1 @and_ranges_overlap_single(i8 %x) {
+; CHECK-LABEL: @and_ranges_overlap_single(
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 6
+; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[X]], -10
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i8 [[TMP3]], 11
+; CHECK-NEXT: [[C7:%.*]] = and i1 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C7]]
+;
+ %c1 = icmp uge i8 %x, 5
+ %c2 = icmp ule i8 %x, 10
+ %c3 = and i1 %c1, %c2
+ %c4 = icmp uge i8 %x, 10
+ %c5 = icmp ule i8 %x, 20
+ %c6 = and i1 %c4, %c5
+ %c7 = and i1 %c3, %c6
+ ret i1 %c7
+}
+
+define i1 @and_ranges_no_overlap(i8 %x) {
+; CHECK-LABEL: @and_ranges_no_overlap(
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 6
+; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[X]], -11
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i8 [[TMP3]], 10
+; CHECK-NEXT: [[C7:%.*]] = and i1 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C7]]
+;
+ %c1 = icmp uge i8 %x, 5
+ %c2 = icmp ule i8 %x, 10
+ %c3 = and i1 %c1, %c2
+ %c4 = icmp uge i8 %x, 11
+ %c5 = icmp ule i8 %x, 20
+ %c6 = and i1 %c4, %c5
+ %c7 = and i1 %c3, %c6
+ ret i1 %c7
+}
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