[PATCH] D113475: [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu created this revision.
zixuan-wu added reviewers: sabuasal, asb, efriedma, apazos.
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Not only RISCV but also other target such as CSKY, there are compressed instructions mixed with normal instructions. To reuse the basic infra to compress/uncompress and predict instruction, we need reconstruct the RISCVCompressInstEmitter and make it more general and suitable for other target.

This patch contains CSKY related part to show the whole picture after the tblgen tool changes, which make review better. It will be removed when it is landed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113475

Files:
  llvm/include/llvm/Target/Target.td
  llvm/lib/Target/CSKY/CMakeLists.txt
  llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp
  llvm/lib/Target/CSKY/CSKYAsmPrinter.h
  llvm/lib/Target/CSKY/CSKYInstrFormats.td
  llvm/lib/Target/CSKY/CSKYInstrInfo16Instr.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
  llvm/lib/Target/RISCV/RISCVInstrInfoC.td
  llvm/test/TableGen/AsmPredicateCombiningRISCV.td
  llvm/utils/TableGen/CMakeLists.txt
  llvm/utils/TableGen/CompressInstEmitter.cpp
  llvm/utils/TableGen/RISCVCompressInstEmitter.cpp

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