[llvm] 5c3c7ad - [CodeGen] Fix assertion failure in TwoAddressInstructionPass::rescheduleMIBelowKill

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-11-09T09:24:21Z
New Revision: 5c3c7adf3a320b2f30bf4b8d86c626d94ae2aafa

URL: https://github.com/llvm/llvm-project/commit/5c3c7adf3a320b2f30bf4b8d86c626d94ae2aafa
DIFF: https://github.com/llvm/llvm-project/commit/5c3c7adf3a320b2f30bf4b8d86c626d94ae2aafa.diff

LOG: [CodeGen] Fix assertion failure in TwoAddressInstructionPass::rescheduleMIBelowKill

This fixes an assertion failure with -early-live-intervals when trying
to update the live intervals for a debug instruction, which don't even
have slot indexes.

Differential Revision: https://reviews.llvm.org/D113116

Added: 
    

Modified: 
    llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index ca7d7e9dbf5f..07e7082767be 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -955,12 +955,13 @@ bool TwoAddressInstructionPass::rescheduleMIBelowKill(
   nmi = End;
   MachineBasicBlock::iterator InsertPos = KillPos;
   if (LIS) {
-    // We have to move the copies first so that the MBB is still well-formed
-    // when calling handleMove().
+    // We have to move the copies (and any interleaved debug instructions)
+    // first so that the MBB is still well-formed when calling handleMove().
     for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
       auto CopyMI = MBBI++;
       MBB->splice(InsertPos, MBB, CopyMI);
-      LIS->handleMove(*CopyMI);
+      if (!CopyMI->isDebugOrPseudoInstr())
+        LIS->handleMove(*CopyMI);
       InsertPos = CopyMI;
     }
     End = std::next(MachineBasicBlock::iterator(MI));

diff  --git a/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir b/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir
index e89e15488a2b..ec452d07c614 100644
--- a/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir
+++ b/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir
@@ -1,6 +1,7 @@
 --- |
   ; REQUIRES: asserts
   ; RUN: llc -start-before=phi-node-elimination -stop-after=machinelicm -debug-only=machinelicm -o - %s  | FileCheck %s
+  ; RUN: llc -start-before=phi-node-elimination -stop-after=machinelicm -debug-only=machinelicm -early-live-intervals -o - %s  | FileCheck %s
   ; Ensure we execute machinelicm post register allocation.
   ; Line numbers should not be retained when loop invariant instructions are hoisted.
   ;