[PATCH] D107210: [RISCV] Support interleaved load lowering

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:997
+  if (!isScalableVector) {
+    auto *FVTy = cast<FixedVectorType>(VTy);
+    SVTy =
----------------
luke957 wrote:
> craig.topper wrote:
> > luke957 wrote:
> > > craig.topper wrote:
> > > > This is not the correct way to convert a fixed vector type to a scalable vector type. For large vectors this will create a type that maps to something larger than LMUL=8. We need to map fixed vector types to scalable vector types using the logic from RISCVTargetLowering::getContainerForFixedLengthVector which takes into account a user provided VLEN via -riscv-v-vector-bits-min command line option.
> > > Em, I'm a little confused here. I understand RISCVTargetLowering::getContainerForFixedLengthVector is used in backend when SDAG is built as this method operates on MVT types. So if we just use opt in the middle-end, is this still needed? Further more, if something larger than LMUL=8 appears, could it be legalized by the backend?
> > All conversions from a fixed vector type to a scalable vector must follow the VLEN passed on the command line in -riscv-v-vector-bits-min. The backend should not be splitting a scalable type if the fixed vector type was supposed to be legal type.
> Yeah, you are right. It takes me some time to understand that. I think we need to make sure the target specific intrinsic is legal according to  the VLEN passed on the command line in -riscv-v-vector-bits-min, so either fixed length vector or scalable vector need legality check (or conversion) for they might exceed the limit of max(LMUL)==8. It seems to be a little bit complicated. Or maybe we could fix this in another patch?
This needs to be handled in this patch. I don't want to think through issues that can arise by not honoring the VLEN correctly.

It might be easier to add fixed vector instrinsics for segment load/store and handle the conversion from fixed vector to scalable vector inside of SelectionDAG where we already have helper functions for the conversion. This is what I did for the RISCVGatherScatterLowering pass which uses masked_strided_load and masked_strided_store intrinsics.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107210/new/

https://reviews.llvm.org/D107210