[PATCH] D113426: [DAGCombiner] add fold for vselect based on mask of signbit, part 3

[Sanjay Patel via Phabricator via llvm-commits]

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(Cond0 s> -1) ? N1 : 0 --> ~(Cond0 s>> BW-1) & N1

https://alive2.llvm.org/ce/z/mGCBrd

This was suggested as a potential enhancement in D113212 <https://reviews.llvm.org/D113212> (also 7e30404c3b6c <https://reviews.llvm.org/rG7e30404c3b6c3610a0d704e8433a3a3134ce982a> ).
This looks like an improvement for AArch that could be generalized ( X > -1 --> X >= 0 ).
For x86, we have a counter-acting fold for most cases that turns the shift+not back into a setcc, so that needs a work-around to get more cases to use "pandn".


https://reviews.llvm.org/D113426

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/vselect-constants.ll
  llvm/test/CodeGen/X86/vselect-zero.ll

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