[llvm] 304edbb - [RISCV] SMUL_LOHI/UMUL_LOHI should expand for RVV.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-11-08T09:38:36-08:00
New Revision: 304edbb553d04341227c8766621e024d6f9fd390

URL: https://github.com/llvm/llvm-project/commit/304edbb553d04341227c8766621e024d6f9fd390
DIFF: https://github.com/llvm/llvm-project/commit/304edbb553d04341227c8766621e024d6f9fd390.diff

LOG: [RISCV] SMUL_LOHI/UMUL_LOHI should expand for RVV.

These and MULHS/MULHU both default to Legal. Targets need to set
the ones they don't support to Expand.

I think MULHS/MULHU likely has priority in most places so this
change probably isn't directly testable. I found it while looking
at disabling MULHS/MULHU for nxvXi64 as required for Zve64x.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D113325

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 372685d4b1e98..9d8d11e8b9807 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -533,6 +533,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
       setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom);
 
+      // Vectors implement MULHS/MULHU.
+      setOperationAction(ISD::SMUL_LOHI, VT, Expand);
+      setOperationAction(ISD::UMUL_LOHI, VT, Expand);
+
       setOperationAction(ISD::SMIN, VT, Legal);
       setOperationAction(ISD::SMAX, VT, Legal);
       setOperationAction(ISD::UMIN, VT, Legal);