[llvm] 3c06920 - [llvm] Use make_early_inc_range (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 8 09:09:48 PST 2021
Author: Kazu Hirata
Date: 2021-11-08T09:09:39-08:00
New Revision: 3c06920cd12f28b63be9d59dc02b50e1815447da
URL: https://github.com/llvm/llvm-project/commit/3c06920cd12f28b63be9d59dc02b50e1815447da
DIFF: https://github.com/llvm/llvm-project/commit/3c06920cd12f28b63be9d59dc02b50e1815447da.diff
LOG: [llvm] Use make_early_inc_range (NFC)
Added:
Modified:
llvm/lib/Bitcode/Reader/BitcodeReader.cpp
llvm/lib/CodeGen/InlineSpiller.cpp
llvm/lib/CodeGen/VirtRegMap.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index 8b0846d6cb6d..c568461e62b0 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -5538,21 +5538,16 @@ Error BitcodeReader::materialize(GlobalValue *GV) {
// Upgrade any old intrinsic calls in the function.
for (auto &I : UpgradedIntrinsics) {
- for (auto UI = I.first->materialized_user_begin(), UE = I.first->user_end();
- UI != UE;) {
- User *U = *UI;
- ++UI;
+ for (User *U : llvm::make_early_inc_range(I.first->materialized_users()))
if (CallInst *CI = dyn_cast<CallInst>(U))
UpgradeIntrinsicCall(CI, I.second);
- }
}
// Update calls to the remangled intrinsics
for (auto &I : RemangledIntrinsics)
- for (auto UI = I.first->materialized_user_begin(), UE = I.first->user_end();
- UI != UE;)
+ for (User *U : llvm::make_early_inc_range(I.first->materialized_users()))
// Don't expect any other users than call sites
- cast<CallBase>(*UI++)->setCalledFunction(I.second);
+ cast<CallBase>(U)->setCalledFunction(I.second);
// Finish fn->subprogram upgrade for materialized functions.
if (DISubprogram *SP = MDLoader->lookupSubprogramForFunction(F))
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index 5b84f8787c9e..64e1f4351456 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -464,10 +464,8 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
LLVM_DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
// Find all spills and copies of VNI.
- for (MachineRegisterInfo::use_instr_nodbg_iterator
- UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
- UI != E; ) {
- MachineInstr &MI = *UI++;
+ for (MachineInstr &MI :
+ llvm::make_early_inc_range(MRI.use_nodbg_instructions(Reg))) {
if (!MI.isCopy() && !MI.mayStore())
continue;
SlotIndex Idx = LIS.getInstructionIndex(MI);
@@ -675,11 +673,7 @@ void InlineSpiller::reMaterializeAll() {
bool anyRemat = false;
for (Register Reg : RegsToSpill) {
LiveInterval &LI = LIS.getInterval(Reg);
- for (MachineRegisterInfo::reg_bundle_iterator
- RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
- RegI != E; ) {
- MachineInstr &MI = *RegI++;
-
+ for (MachineInstr &MI : llvm::make_early_inc_range(MRI.reg_bundles(Reg))) {
// Debug values are not allowed to affect codegen.
if (MI.isDebugValue())
continue;
@@ -1070,57 +1064,53 @@ void InlineSpiller::spillAroundUses(Register Reg) {
LiveInterval &OldLI = LIS.getInterval(Reg);
// Iterate over instructions using Reg.
- for (MachineRegisterInfo::reg_bundle_iterator
- RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
- RegI != E; ) {
- MachineInstr *MI = &*(RegI++);
-
+ for (MachineInstr &MI : llvm::make_early_inc_range(MRI.reg_bundles(Reg))) {
// Debug values are not allowed to affect codegen.
- if (MI->isDebugValue()) {
+ if (MI.isDebugValue()) {
// Modify DBG_VALUE now that the value is in a spill slot.
- MachineBasicBlock *MBB = MI->getParent();
- LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);
- buildDbgValueForSpill(*MBB, MI, *MI, StackSlot, Reg);
+ MachineBasicBlock *MBB = MI.getParent();
+ LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:\t" << MI);
+ buildDbgValueForSpill(*MBB, &MI, MI, StackSlot, Reg);
MBB->erase(MI);
continue;
}
- assert(!MI->isDebugInstr() && "Did not expect to find a use in debug "
+ assert(!MI.isDebugInstr() && "Did not expect to find a use in debug "
"instruction that isn't a DBG_VALUE");
// Ignore copies to/from snippets. We'll delete them.
- if (SnippetCopies.count(MI))
+ if (SnippetCopies.count(&MI))
continue;
// Stack slot accesses may coalesce away.
- if (coalesceStackAccess(MI, Reg))
+ if (coalesceStackAccess(&MI, Reg))
continue;
// Analyze instruction.
SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
- VirtRegInfo RI = AnalyzeVirtRegInBundle(*MI, Reg, &Ops);
+ VirtRegInfo RI = AnalyzeVirtRegInBundle(MI, Reg, &Ops);
// Find the slot index where this instruction reads and writes OldLI.
// This is usually the def slot, except for tied early clobbers.
- SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
+ SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
if (SlotIndex::isSameInstr(Idx, VNI->def))
Idx = VNI->def;
// Check for a sibling copy.
- Register SibReg = isFullCopyOf(*MI, Reg);
+ Register SibReg = isFullCopyOf(MI, Reg);
if (SibReg && isSibling(SibReg)) {
// This may actually be a copy between snippets.
if (isRegToSpill(SibReg)) {
- LLVM_DEBUG(dbgs() << "Found new snippet copy: " << *MI);
- SnippetCopies.insert(MI);
+ LLVM_DEBUG(dbgs() << "Found new snippet copy: " << MI);
+ SnippetCopies.insert(&MI);
continue;
}
if (RI.Writes) {
- if (hoistSpillInsideBB(OldLI, *MI)) {
+ if (hoistSpillInsideBB(OldLI, MI)) {
// This COPY is now dead, the value is already in the stack slot.
- MI->getOperand(0).setIsDead();
- DeadDefs.push_back(MI);
+ MI.getOperand(0).setIsDead();
+ DeadDefs.push_back(&MI);
continue;
}
} else {
@@ -1140,7 +1130,7 @@ void InlineSpiller::spillAroundUses(Register Reg) {
Register NewVReg = Edit->createFrom(Reg);
if (RI.Reads)
- insertReload(NewVReg, Idx, MI);
+ insertReload(NewVReg, Idx, &MI);
// Rewrite instruction operands.
bool hasLiveDef = false;
@@ -1155,12 +1145,12 @@ void InlineSpiller::spillAroundUses(Register Reg) {
hasLiveDef = true;
}
}
- LLVM_DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n');
+ LLVM_DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << MI << '\n');
// FIXME: Use a second vreg if instruction has no tied ops.
if (RI.Writes)
if (hasLiveDef)
- insertSpill(NewVReg, true, MI);
+ insertSpill(NewVReg, true, &MI);
}
}
@@ -1195,10 +1185,8 @@ void InlineSpiller::spillAll() {
// Finally delete the SnippetCopies.
for (Register Reg : RegsToSpill) {
- for (MachineRegisterInfo::reg_instr_iterator
- RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end();
- RI != E; ) {
- MachineInstr &MI = *(RI++);
+ for (MachineInstr &MI :
+ llvm::make_early_inc_range(MRI.reg_instructions(Reg))) {
assert(SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy");
// FIXME: Do this with a LiveRangeEdit callback.
LIS.RemoveMachineInstrFromMaps(MI);
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 0f164e2637a2..61ddba9403cd 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -541,13 +541,10 @@ void VirtRegRewriter::rewrite() {
for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
MBBI != MBBE; ++MBBI) {
LLVM_DEBUG(MBBI->print(dbgs(), Indexes));
- for (MachineBasicBlock::instr_iterator
- MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
- MachineInstr *MI = &*MII;
- ++MII;
-
- for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
- MOE = MI->operands_end(); MOI != MOE; ++MOI) {
+ for (MachineInstr &MI : llvm::make_early_inc_range(MBBI->instrs())) {
+ for (MachineInstr::mop_iterator MOI = MI.operands_begin(),
+ MOE = MI.operands_end();
+ MOI != MOE; ++MOI) {
MachineOperand &MO = *MOI;
// Make sure MRI knows about registers clobbered by regmasks.
@@ -574,7 +571,7 @@ void VirtRegRewriter::rewrite() {
// have to add implicit killed operands for the super-register. A
// partial redef always kills and redefines the super-register.
if ((MO.readsReg() && (MO.isDef() || MO.isKill())) ||
- (MO.isDef() && subRegLiveThrough(*MI, PhysReg)))
+ (MO.isDef() && subRegLiveThrough(MI, PhysReg)))
SuperKills.push_back(PhysReg);
if (MO.isDef()) {
@@ -619,20 +616,20 @@ void VirtRegRewriter::rewrite() {
// Add any missing super-register kills after rewriting the whole
// instruction.
while (!SuperKills.empty())
- MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
+ MI.addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
while (!SuperDeads.empty())
- MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
+ MI.addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
while (!SuperDefs.empty())
- MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
+ MI.addRegisterDefined(SuperDefs.pop_back_val(), TRI);
- LLVM_DEBUG(dbgs() << "> " << *MI);
+ LLVM_DEBUG(dbgs() << "> " << MI);
- expandCopyBundle(*MI);
+ expandCopyBundle(MI);
// We can remove identity copies right now.
- handleIdentityCopy(*MI);
+ handleIdentityCopy(MI);
}
}
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