[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

[Filipp Zhinkin via Phabricator via llvm-commits]

fzhinkin added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:4153
       // all bits clear: (X | (Y<<32)) ==  0 --> (X | Y) ==  0
       // all bits set:   (X | (Y<<32)) == -1 --> (X & Y) == -1
       bool CmpZero = N1C->getAPIntValue().isZero();
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RKSimon wrote:
> This is doing something pretty similar, its more limited to the 'concat' pattern but handles the -1 'allbits' case as well.
Are you suggesting to extract and reuse code common to both optimizations or to support `-1` in `optimizeSetCCOfExpandedShift`?


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Comment at: llvm/test/CodeGen/ARM/icmp-shift-opt.ll:150
+   ret i1 %cmp
+}
+
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RKSimon wrote:
> sorry - I didn't add this one - I'll commit this shortly.
Thank you.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D111530/new/

https://reviews.llvm.org/D111530