[llvm] 4ed1327 - [ARM] Precommit i128 test from D111530

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-11-08T16:08:21Z
New Revision: 4ed13275b73c33d757cb108d1a7c11a7f016ab58

URL: https://github.com/llvm/llvm-project/commit/4ed13275b73c33d757cb108d1a7c11a7f016ab58
DIFF: https://github.com/llvm/llvm-project/commit/4ed13275b73c33d757cb108d1a7c11a7f016ab58.diff

LOG: [ARM] Precommit i128 test from D111530

Added: 
    

Modified: 
    llvm/test/CodeGen/ARM/icmp-shift-opt.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/ARM/icmp-shift-opt.ll b/llvm/test/CodeGen/ARM/icmp-shift-opt.ll
index d2514b160801..1d0701875ced 100644
--- a/llvm/test/CodeGen/ARM/icmp-shift-opt.ll
+++ b/llvm/test/CodeGen/ARM/icmp-shift-opt.ll
@@ -148,4 +148,23 @@ define i1 @opt_setcc_expanded_shl_wrong_shifts(i32 %a, i32 %b) nounwind {
   ret i1 %cmp
 }
 
+define i1 @opt_setcc_shl_ne_zero_i128(i128 %a) nounwind {
+; CHECK-LABEL: opt_setcc_shl_ne_zero_i128:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    lsl r3, r3, #17
+; CHECK-NEXT:    orr r12, r3, r2, lsr #15
+; CHECK-NEXT:    lsl r3, r1, #17
+; CHECK-NEXT:    lsl r2, r2, #17
+; CHECK-NEXT:    orr r3, r3, r0, lsr #15
+; CHECK-NEXT:    orr r1, r2, r1, lsr #15
+; CHECK-NEXT:    orr r3, r3, r12
+; CHECK-NEXT:    orr r0, r1, r0, lsl #17
+; CHECK-NEXT:    orrs r0, r0, r3
+; CHECK-NEXT:    movwne r0, #1
+; CHECK-NEXT:    bx lr
+  %shl = shl i128 %a, 17
+  %cmp = icmp ne i128 %shl, 0
+  ret i1 %cmp
+}
+
 declare void @use(i64 %a)