[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

[Filipp Zhinkin via Phabricator via llvm-commits]

fzhinkin added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/icmp-shift-opt.ll:151
+   ret i1 %cmp
+}
+
----------------
fzhinkin wrote:
> RKSimon wrote:
> > pre-commit?
> Will appreciate if you can help me with committing it: {F20154245}
thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111530/new/

https://reviews.llvm.org/D111530