[llvm] fba1f36 - [Test][SCCP] Precommit tests for PR52253
Anton Afanasyev via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 8 06:00:27 PST 2021
Author: Anton Afanasyev
Date: 2021-11-08T16:59:38+03:00
New Revision: fba1f36d138cd50eb313d77cd538724f09287214
URL: https://github.com/llvm/llvm-project/commit/fba1f36d138cd50eb313d77cd538724f09287214
DIFF: https://github.com/llvm/llvm-project/commit/fba1f36d138cd50eb313d77cd538724f09287214.diff
LOG: [Test][SCCP] Precommit tests for PR52253
Added:
llvm/test/Transforms/PhaseOrdering/X86/pr52253.ll
llvm/test/Transforms/SCCP/overdefined-ext.ll
llvm/test/Transforms/SCCP/pr52253.ll
Modified:
llvm/test/Transforms/SCCP/ip-ranges-casts.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/pr52253.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr52253.ll
new file mode 100644
index 000000000000..ba2fd6596270
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/pr52253.ll
@@ -0,0 +1,93 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -O3 -S < %s | FileCheck %s
+; RUN: opt -instcombine -sccp -bdce -S < %s | FileCheck %s
+; RUN: opt -aggressive-instcombine -instcombine -sccp -bdce -S < %s | FileCheck %s --check-prefix=AIC_FIRST
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i1 @foo(i32 %t4, i32 %t10) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: ret i1 false
+;
+; AIC_FIRST-LABEL: @foo(
+; AIC_FIRST-NEXT: ret i1 false
+;
+ %t09 = shl i32 %t10, 24
+ %t010 = ashr exact i32 %t09, 24
+ %t011 = add nsw i32 %t010, 979
+ %t11 = trunc i32 %t4 to i8
+ %t12 = icmp eq i8 %t11, 0
+ %t14 = zext i1 %t12 to i32
+ %t15 = shl i32 %t4, %t14
+ %t17 = and i32 %t15, 255
+ %t18 = icmp eq i32 %t011, %t17
+ ret i1 %t18
+}
+
+define i1 @bar(i32 %t4, i32 %t10) {
+; CHECK-LABEL: @bar(
+; CHECK-NEXT: [[T09:%.*]] = shl i32 [[T10:%.*]], 24
+; CHECK-NEXT: [[T010:%.*]] = ashr exact i32 [[T09]], 24
+; CHECK-NEXT: [[T011:%.*]] = add nsw i32 [[T010]], 979
+; CHECK-NEXT: [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
+; CHECK-NEXT: [[T12:%.*]] = icmp eq i8 [[T11]], 0
+; CHECK-NEXT: [[T14:%.*]] = zext i1 [[T12]] to i8
+; CHECK-NEXT: [[T15:%.*]] = shl i8 [[T11]], [[T14]]
+; CHECK-NEXT: [[T17:%.*]] = zext i8 [[T15]] to i32
+; CHECK-NEXT: [[T18:%.*]] = icmp eq i32 [[T011]], [[T17]]
+; CHECK-NEXT: ret i1 [[T18]]
+;
+; AIC_FIRST-LABEL: @bar(
+; AIC_FIRST-NEXT: [[T09:%.*]] = shl i32 [[T10:%.*]], 24
+; AIC_FIRST-NEXT: [[T010:%.*]] = ashr exact i32 [[T09]], 24
+; AIC_FIRST-NEXT: [[T011:%.*]] = add nsw i32 [[T010]], 979
+; AIC_FIRST-NEXT: [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
+; AIC_FIRST-NEXT: [[T12:%.*]] = icmp eq i8 [[T11]], 0
+; AIC_FIRST-NEXT: [[T14:%.*]] = zext i1 [[T12]] to i8
+; AIC_FIRST-NEXT: [[T15:%.*]] = shl i8 [[T11]], [[T14]]
+; AIC_FIRST-NEXT: [[T17:%.*]] = zext i8 [[T15]] to i32
+; AIC_FIRST-NEXT: [[T18:%.*]] = icmp eq i32 [[T011]], [[T17]]
+; AIC_FIRST-NEXT: ret i1 [[T18]]
+;
+ %t09 = shl i32 %t10, 24
+ %t010 = ashr exact i32 %t09, 24
+ %t011 = add nsw i32 %t010, 979
+ %t11 = trunc i32 %t4 to i8
+ %t12 = icmp eq i8 %t11, 0
+ %t14 = zext i1 %t12 to i8
+ %t15 = shl i8 %t11, %t14
+ %t17 = zext i8 %t15 to i32
+ %t18 = icmp eq i32 %t011, %t17
+ ret i1 %t18
+}
+
+define i1 @foobar(i32 %t4, i32 %t10) {
+; CHECK-LABEL: @foobar(
+; CHECK-NEXT: ret i1 false
+;
+; AIC_FIRST-LABEL: @foobar(
+; AIC_FIRST-NEXT: [[T09:%.*]] = shl i32 [[T10:%.*]], 24
+; AIC_FIRST-NEXT: [[T010:%.*]] = ashr exact i32 [[T09]], 24
+; AIC_FIRST-NEXT: [[T011:%.*]] = add nsw i32 [[T010]], 979
+; AIC_FIRST-NEXT: [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
+; AIC_FIRST-NEXT: [[T12:%.*]] = icmp eq i8 [[T11]], 0
+; AIC_FIRST-NEXT: [[T14:%.*]] = zext i1 [[T12]] to i8
+; AIC_FIRST-NEXT: [[T15:%.*]] = shl i8 [[T11]], [[T14]]
+; AIC_FIRST-NEXT: [[T17:%.*]] = zext i8 [[T15]] to i32
+; AIC_FIRST-NEXT: [[T18:%.*]] = icmp eq i32 [[T011]], [[T17]]
+; AIC_FIRST-NEXT: ret i1 [[T18]]
+;
+ %t09 = shl i32 %t10, 24
+ %t010 = ashr exact i32 %t09, 24
+ %t011 = add nsw i32 %t010, 979
+ %t11 = trunc i32 %t4 to i8
+ %t12 = icmp eq i8 %t11, 0
+ %t13 = zext i8 %t11 to i32
+ %t14 = select i1 %t12, i32 1, i32 0
+ %t15 = shl nuw nsw i32 %t13, %t14
+ %t16 = trunc i32 %t15 to i8
+ %t17 = zext i8 %t16 to i32
+ %t18 = icmp eq i32 %t011, %t17
+ ret i1 %t18
+}
diff --git a/llvm/test/Transforms/SCCP/ip-ranges-casts.ll b/llvm/test/Transforms/SCCP/ip-ranges-casts.ll
index 76aa415f62bb..c20c7e218741 100644
--- a/llvm/test/Transforms/SCCP/ip-ranges-casts.ll
+++ b/llvm/test/Transforms/SCCP/ip-ranges-casts.ll
@@ -315,3 +315,25 @@ entry:
%1 = trunc i128 %0 to i16
ret i16 %1
}
+
+define internal i64 @f.sext_to_zext(i32 %t) {
+; CHECK-LABEL: @f.sext_to_zext(
+; CHECK-NEXT: [[A:%.*]] = sext i32 [[T:%.*]] to i64
+; CHECK-NEXT: ret i64 [[A]]
+;
+ %a = sext i32 %t to i64
+ ret i64 %a
+}
+
+define i64 @caller.sext_to_zext(i32 %i) {
+; CHECK-LABEL: @caller.sext_to_zext(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[I:%.*]], 9
+; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32
+; CHECK-NEXT: [[T:%.*]] = call i64 @f.sext_to_zext(i32 [[CONV]])
+; CHECK-NEXT: ret i64 [[T]]
+;
+ %cmp = icmp sle i32 %i, 9
+ %conv = zext i1 %cmp to i32
+ %t = call i64 @f.sext_to_zext(i32 %conv)
+ ret i64 %t
+}
diff --git a/llvm/test/Transforms/SCCP/overdefined-ext.ll b/llvm/test/Transforms/SCCP/overdefined-ext.ll
new file mode 100644
index 000000000000..f855e636a2a1
--- /dev/null
+++ b/llvm/test/Transforms/SCCP/overdefined-ext.ll
@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -sccp -S | FileCheck %s
+
+define i32 @zext_lshr(i1 %t0) {
+; CHECK-LABEL: @zext_lshr(
+; CHECK-NEXT: [[T1:%.*]] = zext i1 [[T0:%.*]] to i32
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], 1
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t1 = zext i1 %t0 to i32
+ %t2 = lshr i32 %t1, 1
+ ret i32 %t2
+}
+
+define i1 @zext_icmp(i1 %t0) {
+; CHECK-LABEL: @zext_icmp(
+; CHECK-NEXT: [[T1:%.*]] = zext i1 [[T0:%.*]] to i32
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 2
+; CHECK-NEXT: ret i1 [[T2]]
+;
+ %t1 = zext i1 %t0 to i32
+ %t2 = icmp eq i32 %t1, 2
+ ret i1 %t2
+}
+
+define <2 x i1> @zext_vector(<2 x i1> %t0) {
+; CHECK-LABEL: @zext_vector(
+; CHECK-NEXT: [[T1:%.*]] = zext <2 x i1> [[T0:%.*]] to <2 x i32>
+; CHECK-NEXT: [[T2:%.*]] = icmp eq <2 x i32> [[T1]], <i32 2, i32 2>
+; CHECK-NEXT: ret <2 x i1> [[T2]]
+;
+ %t1 = zext <2 x i1> %t0 to <2 x i32>
+ %t2 = icmp eq <2 x i32> %t1, <i32 2, i32 2>
+ ret <2 x i1> %t2
+}
+
+define <2 x i1> @zext_vector2(<2 x i1> %t0) {
+; CHECK-LABEL: @zext_vector2(
+; CHECK-NEXT: [[T1:%.*]] = zext <2 x i1> [[T0:%.*]] to <2 x i32>
+; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[T1]], <i32 2, i32 2>
+; CHECK-NEXT: [[T3:%.*]] = icmp eq <2 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <2 x i1> [[T3]]
+;
+ %t1 = zext <2 x i1> %t0 to <2 x i32>
+ %t2 = add <2 x i32> %t1, <i32 2, i32 2>
+ %t3 = icmp eq <2 x i32> %t1, %t2
+ ret <2 x i1> %t3
+}
+
+define i32 @sext_ashr(i1 %t0) {
+; CHECK-LABEL: @sext_ashr(
+; CHECK-NEXT: [[T1:%.*]] = sext i1 [[T0:%.*]] to i32
+; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[T1]], 1
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t1 = sext i1 %t0 to i32
+ %t2 = ashr i32 %t1, 1
+ ret i32 %t2
+}
+
+define i1 @sext_icmp(i1 %t0) {
+; CHECK-LABEL: @sext_icmp(
+; CHECK-NEXT: [[T1:%.*]] = sext i1 [[T0:%.*]] to i32
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 2
+; CHECK-NEXT: ret i1 [[T2]]
+;
+ %t1 = sext i1 %t0 to i32
+ %t2 = icmp eq i32 %t1, 2
+ ret i1 %t2
+}
+
+define <2 x i1> @sext_vector(<2 x i1> %t0) {
+; CHECK-LABEL: @sext_vector(
+; CHECK-NEXT: [[T1:%.*]] = sext <2 x i1> [[T0:%.*]] to <2 x i32>
+; CHECK-NEXT: [[T2:%.*]] = icmp eq <2 x i32> [[T1]], <i32 2, i32 2>
+; CHECK-NEXT: ret <2 x i1> [[T2]]
+;
+ %t1 = sext <2 x i1> %t0 to <2 x i32>
+ %t2 = icmp eq <2 x i32> %t1, <i32 2, i32 2>
+ ret <2 x i1> %t2
+}
+
+define <2 x i1> @sext_vector2(<2 x i1> %t0) {
+; CHECK-LABEL: @sext_vector2(
+; CHECK-NEXT: [[T1:%.*]] = sext <2 x i1> [[T0:%.*]] to <2 x i32>
+; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[T1]], <i32 2, i32 2>
+; CHECK-NEXT: [[T3:%.*]] = icmp eq <2 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <2 x i1> [[T3]]
+;
+ %t1 = sext <2 x i1> %t0 to <2 x i32>
+ %t2 = add <2 x i32> %t1, <i32 2, i32 2>
+ %t3 = icmp eq <2 x i32> %t1, %t2
+ ret <2 x i1> %t3
+}
diff --git a/llvm/test/Transforms/SCCP/pr52253.ll b/llvm/test/Transforms/SCCP/pr52253.ll
new file mode 100644
index 000000000000..0088eebfdf11
--- /dev/null
+++ b/llvm/test/Transforms/SCCP/pr52253.ll
@@ -0,0 +1,82 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -sccp -S | FileCheck %s
+
+define i1 @foo(i32 %t4, i32 %t10) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: [[T09:%.*]] = shl i32 [[T10:%.*]], 24
+; CHECK-NEXT: [[T010:%.*]] = ashr exact i32 [[T09]], 24
+; CHECK-NEXT: [[T011:%.*]] = add nsw i32 [[T010]], 979
+; CHECK-NEXT: [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
+; CHECK-NEXT: [[T12:%.*]] = icmp eq i8 [[T11]], 0
+; CHECK-NEXT: [[T14:%.*]] = zext i1 [[T12]] to i32
+; CHECK-NEXT: [[T15:%.*]] = shl i32 [[T4]], [[T14]]
+; CHECK-NEXT: [[T17:%.*]] = and i32 [[T15]], 255
+; CHECK-NEXT: ret i1 false
+;
+ %t09 = shl i32 %t10, 24
+ %t010 = ashr exact i32 %t09, 24
+ %t011 = add nsw i32 %t010, 979
+ %t11 = trunc i32 %t4 to i8
+ %t12 = icmp eq i8 %t11, 0
+ %t14 = zext i1 %t12 to i32
+ %t15 = shl i32 %t4, %t14
+ %t17 = and i32 %t15, 255
+ %t18 = icmp eq i32 %t011, %t17
+ ret i1 %t18
+}
+
+define i1 @bar(i32 %t4, i32 %t10) {
+; CHECK-LABEL: @bar(
+; CHECK-NEXT: [[T09:%.*]] = shl i32 [[T10:%.*]], 24
+; CHECK-NEXT: [[T010:%.*]] = ashr exact i32 [[T09]], 24
+; CHECK-NEXT: [[T011:%.*]] = add nsw i32 [[T010]], 979
+; CHECK-NEXT: [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
+; CHECK-NEXT: [[T12:%.*]] = icmp eq i8 [[T11]], 0
+; CHECK-NEXT: [[T14:%.*]] = zext i1 [[T12]] to i8
+; CHECK-NEXT: [[T15:%.*]] = shl i8 [[T11]], [[T14]]
+; CHECK-NEXT: [[T17:%.*]] = zext i8 [[T15]] to i32
+; CHECK-NEXT: [[T18:%.*]] = icmp eq i32 [[T011]], [[T17]]
+; CHECK-NEXT: ret i1 [[T18]]
+;
+ %t09 = shl i32 %t10, 24
+ %t010 = ashr exact i32 %t09, 24
+ %t011 = add nsw i32 %t010, 979
+ %t11 = trunc i32 %t4 to i8
+ %t12 = icmp eq i8 %t11, 0
+ %t14 = zext i1 %t12 to i8
+ %t15 = shl i8 %t11, %t14
+ %t17 = zext i8 %t15 to i32
+ %t18 = icmp eq i32 %t011, %t17
+ ret i1 %t18
+}
+
+define i1 @foobar(i32 %t4, i32 %t10) {
+; CHECK-LABEL: @foobar(
+; CHECK-NEXT: [[T09:%.*]] = shl i32 [[T10:%.*]], 24
+; CHECK-NEXT: [[T010:%.*]] = ashr exact i32 [[T09]], 24
+; CHECK-NEXT: [[T011:%.*]] = add nsw i32 [[T010]], 979
+; CHECK-NEXT: [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
+; CHECK-NEXT: [[T12:%.*]] = icmp eq i8 [[T11]], 0
+; CHECK-NEXT: [[T13:%.*]] = zext i8 [[T11]] to i32
+; CHECK-NEXT: [[T14:%.*]] = select i1 [[T12]], i32 1, i32 0
+; CHECK-NEXT: [[T15:%.*]] = shl nuw nsw i32 [[T13]], [[T14]]
+; CHECK-NEXT: [[T16:%.*]] = trunc i32 [[T15]] to i8
+; CHECK-NEXT: [[T17:%.*]] = zext i8 [[T16]] to i32
+; CHECK-NEXT: [[T18:%.*]] = icmp eq i32 [[T011]], [[T17]]
+; CHECK-NEXT: ret i1 [[T18]]
+;
+ %t09 = shl i32 %t10, 24
+ %t010 = ashr exact i32 %t09, 24
+ %t011 = add nsw i32 %t010, 979
+
+ %t11 = trunc i32 %t4 to i8
+ %t12 = icmp eq i8 %t11, 0
+ %t13 = zext i8 %t11 to i32
+ %t14 = select i1 %t12, i32 1, i32 0
+ %t15 = shl nuw nsw i32 %t13, %t14
+ %t16 = trunc i32 %t15 to i8
+ %t17 = zext i8 %t16 to i32
+
+ %t18 = icmp eq i32 %t011, %t17
+ ret i1 %t18
+}
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