[PATCH] D113376: [AArch64][SVE] Lower shuffles to permute instructions: zip1/2, uzp1/2, trn1/2

Mon Nov 8 05:13:48 PST 2021

paulwalker-arm requested changes to this revision.
paulwalker-arm added inline comments.
This revision now requires changes to proceed.

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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9678-9681
+  if (isZIPMask(M, VT, WhichResult)) {
+    unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
+    return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
+  }
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I don't believe this logic is universally safe.  The use of ZIP2 specifically relies on knowing the exact size of the register to know which indices represent the "high half" of a vector register.  This is something that is only known when `sve-vector-bits-min==sve-vector-bits-max`.

I also suspect functions like isZIPMask were written when only 64 and 128 bit legal vectors existed.  I doubt the logic holds for the case when a vector is legal but not the exact size of the target vector register, as is the case with the SVE fixed length support.

I have not looked into the extent at which the other shuffles are affected but I suspect each have their own complexity.

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Comment at: llvm/test/CodeGen/AArch64/sve-fix-length-permute-zip-uzp-trn.ll:21
+  %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47>
+  %tmp4 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> <i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>
+  %tmp5 = add <32 x i8> %tmp3, %tmp4
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To highlight my previous comment. Index `16` is only the first byte of the second half of a 256bit vector and thus if the target has bigger vector register the use of `zip2` will not have the correct behaviour.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113376/new/

https://reviews.llvm.org/D113376