[PATCH] D112692: [RISCV] Generate pseudo instruction li

Jessica Clarke via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Nov 1 05:34:25 PDT 2021


jrtc27 added a comment.

In D112692#3099685 <https://reviews.llvm.org/D112692#3099685>, @pcwang-thead wrote:

> Change addi/mv zero in compiler-rt to li

This is a completely separate thing, it does not belong here (and I don't agree that it's better, it's just different, they're both idiomatic)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112692/new/

https://reviews.llvm.org/D112692



More information about the llvm-commits mailing list