[llvm] 7c6f595 - [PowerPC] comment for different input register classes; nfc

[Chen Zheng via llvm-commits]

Author: Chen Zheng
Date: 2021-11-08T02:21:30Z
New Revision: 7c6f5950f08d41017536575152fb765ba85a09a1

URL: https://github.com/llvm/llvm-project/commit/7c6f5950f08d41017536575152fb765ba85a09a1
DIFF: https://github.com/llvm/llvm-project/commit/7c6f5950f08d41017536575152fb765ba85a09a1.diff

LOG: [PowerPC] comment for different input register classes; nfc

Add comments to explain why XXPERMDIs and XXPERMDI have different input register
classes, vsfrc for XXPERMDIs and vsrc for XXPERMDI.

This addresses the comments in abandoned patch D113178, we keep using `f0` instead
of using `vs0` for XXPERMDIs on purpose.

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrVSX.td

Removed: 
    


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diff  --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 03ce0315a5c9f..506c7fa1bfd04 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1066,6 +1066,14 @@ let hasSideEffects = 0 in {
                        [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,
                          imm32SExt16:$DM))]>;
   let isCodeGenOnly = 1 in
+  // Note that the input register class for `$XA` of XXPERMDIs is `vsfrc` which
+  // is not the same with the input register class(`vsrc`) of XXPERMDI instruction.
+  // We did this on purpose because:
+  // 1: The input is primarily for loads that load a partial vector(LFIWZX,
+  //    etc.), no need for SUBREG_TO_REG.
+  // 2: With `vsfrc` register class, in the final assembly, float registers
+  //    like `f0` are used instead of vector scalar register like `vs0`. This
+  //    helps readability.
   def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
                              "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
   def XXSEL : XX4Form<60, 3,