[llvm] 17acd6d - [AArch64] Rewrite and update fcvt-fixed.ll. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 7 10:11:54 PST 2021
Author: David Green
Date: 2021-11-07T18:11:49Z
New Revision: 17acd6d9403ac50c678efdc1ae74f6a7b107e129
URL: https://github.com/llvm/llvm-project/commit/17acd6d9403ac50c678efdc1ae74f6a7b107e129
DIFF: https://github.com/llvm/llvm-project/commit/17acd6d9403ac50c678efdc1ae74f6a7b107e129.diff
LOG: [AArch64] Rewrite and update fcvt-fixed.ll. NFC
This rewrites the fcvt-fixed.ll test case to be separate functions, not
one large function with volatile global stores. It also adds fp16 and
fptoi.sat testing at the same time.
Added:
Modified:
llvm/test/CodeGen/AArch64/fcvt-fixed.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/fcvt-fixed.ll b/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
index ccb3616b70bfa..05e9e6f20ce68 100644
--- a/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
@@ -1,195 +1,1060 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 -O0
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-NO16
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
-; (The O0 test is to make sure FastISel still constrains its operands properly
-; and the verifier doesn't trigger).
+; fptoui
- at var32 = global i32 0
- at var64 = global i64 0
+define i32 @fcvtzs_f32_i32_7(float %flt) {
+; CHECK-LABEL: fcvtzs_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, s0, #7
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 128.0
+ %cvt = fptosi float %fix to i32
+ ret i32 %cvt
+}
+
+define i32 @fcvtzs_f32_i32_32(float %flt) {
+; CHECK-LABEL: fcvtzs_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, s0, #32
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 4294967296.0
+ %cvt = fptosi float %fix to i32
+ ret i32 %cvt
+}
+
+define i64 @fcvtzs_f32_i64_7(float %flt) {
+; CHECK-LABEL: fcvtzs_f32_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, s0, #7
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 128.0
+ %cvt = fptosi float %fix to i64
+ ret i64 %cvt
+}
+
+define i64 @fcvtzs_f32_i64_64(float %flt) {
+; CHECK-LABEL: fcvtzs_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, s0, #64
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 18446744073709551616.0
+ %cvt = fptosi float %fix to i64
+ ret i64 %cvt
+}
+
+define i32 @fcvtzs_f64_i32_7(double %dbl) {
+; CHECK-LABEL: fcvtzs_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, d0, #7
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 128.0
+ %cvt = fptosi double %fix to i32
+ ret i32 %cvt
+}
+
+define i32 @fcvtzs_f64_i32_32(double %dbl) {
+; CHECK-LABEL: fcvtzs_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs w0, d0, #32
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 4294967296.0
+ %cvt = fptosi double %fix to i32
+ ret i32 %cvt
+}
+
+define i64 @fcvtzs_f64_i64_7(double %dbl) {
+; CHECK-LABEL: fcvtzs_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, d0, #7
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 128.0
+ %cvt = fptosi double %fix to i64
+ ret i64 %cvt
+}
+
+define i64 @fcvtzs_f64_i64_64(double %dbl) {
+; CHECK-LABEL: fcvtzs_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x0, d0, #64
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 18446744073709551616.0
+ %cvt = fptosi double %fix to i64
+ ret i64 %cvt
+}
+
+define i32 @fcvtzs_f16_i32_7(half %flt) {
+; CHECK-NO16-LABEL: fcvtzs_f16_i32_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzs w0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzs_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs w0, h0, #7
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %flt, 128.0
+ %cvt = fptosi half %fix to i32
+ ret i32 %cvt
+}
+
+define i32 @fcvtzs_f16_i32_15(half %flt) {
+; CHECK-NO16-LABEL: fcvtzs_f16_i32_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzs w0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzs_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs w0, h0, #15
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %flt, 32768.0
+ %cvt = fptosi half %fix to i32
+ ret i32 %cvt
+}
+
+define i64 @fcvtzs_f16_i64_7(half %flt) {
+; CHECK-NO16-LABEL: fcvtzs_f16_i64_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzs x0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzs_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs x0, h0, #7
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %flt, 128.0
+ %cvt = fptosi half %fix to i64
+ ret i64 %cvt
+}
+
+define i64 @fcvtzs_f16_i64_15(half %flt) {
+; CHECK-NO16-LABEL: fcvtzs_f16_i64_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzs x0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzs_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs x0, h0, #15
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %flt, 32768.0
+ %cvt = fptosi half %fix to i64
+ ret i64 %cvt
+}
+
+; fptoui
+
+define i32 @fcvtzu_f32_i32_7(float %flt) {
+; CHECK-LABEL: fcvtzu_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, s0, #7
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 128.0
+ %cvt = fptoui float %fix to i32
+ ret i32 %cvt
+}
+
+define i32 @fcvtzu_f32_i32_32(float %flt) {
+; CHECK-LABEL: fcvtzu_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, s0, #32
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 4294967296.0
+ %cvt = fptoui float %fix to i32
+ ret i32 %cvt
+}
+
+define i64 @fcvtzu_f32_i64_7(float %flt) {
+; CHECK-LABEL: fcvtzu_f32_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, s0, #7
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 128.0
+ %cvt = fptoui float %fix to i64
+ ret i64 %cvt
+}
+
+define i64 @fcvtzu_f32_i64_64(float %flt) {
+; CHECK-LABEL: fcvtzu_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, s0, #64
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 18446744073709551616.0
+ %cvt = fptoui float %fix to i64
+ ret i64 %cvt
+}
+
+define i32 @fcvtzu_f64_i32_7(double %dbl) {
+; CHECK-LABEL: fcvtzu_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, d0, #7
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 128.0
+ %cvt = fptoui double %fix to i32
+ ret i32 %cvt
+}
-define void @test_fcvtzs(float %flt, double %dbl) {
-; CHECK-LABEL: test_fcvtzs:
+define i32 @fcvtzu_f64_i32_32(double %dbl) {
+; CHECK-LABEL: fcvtzu_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu w0, d0, #32
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 4294967296.0
+ %cvt = fptoui double %fix to i32
+ ret i32 %cvt
+}
+
+define i64 @fcvtzu_f64_i64_7(double %dbl) {
+; CHECK-LABEL: fcvtzu_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, d0, #7
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 128.0
+ %cvt = fptoui double %fix to i64
+ ret i64 %cvt
+}
+
+define i64 @fcvtzu_f64_i64_64(double %dbl) {
+; CHECK-LABEL: fcvtzu_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x0, d0, #64
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 18446744073709551616.0
+ %cvt = fptoui double %fix to i64
+ ret i64 %cvt
+}
+
+define i32 @fcvtzu_f16_i32_7(half %flt) {
+; CHECK-NO16-LABEL: fcvtzu_f16_i32_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzu w0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzu_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu w0, h0, #7
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %flt, 128.0
+ %cvt = fptoui half %fix to i32
+ ret i32 %cvt
+}
+
+define i32 @fcvtzu_f16_i32_15(half %flt) {
+; CHECK-NO16-LABEL: fcvtzu_f16_i32_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzu w0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzu_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu w0, h0, #15
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %flt, 32768.0
+ %cvt = fptoui half %fix to i32
+ ret i32 %cvt
+}
+
+define i64 @fcvtzu_f16_i64_7(half %flt) {
+; CHECK-NO16-LABEL: fcvtzu_f16_i64_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzu x0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzu_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu x0, h0, #7
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %flt, 128.0
+ %cvt = fptoui half %fix to i64
+ ret i64 %cvt
+}
+
+define i64 @fcvtzu_f16_i64_15(half %flt) {
+; CHECK-NO16-LABEL: fcvtzu_f16_i64_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzu x0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzu_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu x0, h0, #15
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %flt, 32768.0
+ %cvt = fptoui half %fix to i64
+ ret i64 %cvt
+}
+
+; sitofp
+
+define float @scvtf_f32_i32_7(i32 %int) {
+; CHECK-LABEL: scvtf_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf s0, w0, #7
+; CHECK-NEXT: ret
+ %cvt = sitofp i32 %int to float
+ %fix = fdiv float %cvt, 128.0
+ ret float %fix
+}
+
+define float @scvtf_f32_i32_32(i32 %int) {
+; CHECK-LABEL: scvtf_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf s0, w0, #32
+; CHECK-NEXT: ret
+ %cvt = sitofp i32 %int to float
+ %fix = fdiv float %cvt, 4294967296.0
+ ret float %fix
+}
- %fix1 = fmul float %flt, 128.0
- %cvt1 = fptosi float %fix1 to i32
-; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #7
- store volatile i32 %cvt1, i32* @var32
+define float @scvtf_f32_i64_7(i64 %long) {
+; CHECK-LABEL: scvtf_f32_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf s0, x0, #7
+; CHECK-NEXT: ret
+ %cvt = sitofp i64 %long to float
+ %fix = fdiv float %cvt, 128.0
+ ret float %fix
+}
- %fix2 = fmul float %flt, 4294967296.0
- %cvt2 = fptosi float %fix2 to i32
-; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #32
- store volatile i32 %cvt2, i32* @var32
+define float @scvtf_f32_i64_64(i64 %long) {
+; CHECK-LABEL: scvtf_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf s0, x0, #64
+; CHECK-NEXT: ret
+ %cvt = sitofp i64 %long to float
+ %fix = fdiv float %cvt, 18446744073709551616.0
+ ret float %fix
+}
- %fix3 = fmul float %flt, 128.0
- %cvt3 = fptosi float %fix3 to i64
-; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #7
- store volatile i64 %cvt3, i64* @var64
+define double @scvtf_f64_i32_7(i32 %int) {
+; CHECK-LABEL: scvtf_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf d0, w0, #7
+; CHECK-NEXT: ret
+ %cvt = sitofp i32 %int to double
+ %fix = fdiv double %cvt, 128.0
+ ret double %fix
+}
- %fix4 = fmul float %flt, 18446744073709551616.0
- %cvt4 = fptosi float %fix4 to i64
-; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #64
- store volatile i64 %cvt4, i64* @var64
-
- %fix5 = fmul double %dbl, 128.0
- %cvt5 = fptosi double %fix5 to i32
-; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #7
- store volatile i32 %cvt5, i32* @var32
-
- %fix6 = fmul double %dbl, 4294967296.0
- %cvt6 = fptosi double %fix6 to i32
-; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #32
- store volatile i32 %cvt6, i32* @var32
-
- %fix7 = fmul double %dbl, 128.0
- %cvt7 = fptosi double %fix7 to i64
-; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #7
- store volatile i64 %cvt7, i64* @var64
-
- %fix8 = fmul double %dbl, 18446744073709551616.0
- %cvt8 = fptosi double %fix8 to i64
-; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #64
- store volatile i64 %cvt8, i64* @var64
-
- ret void
+define double @scvtf_f64_i32_32(i32 %int) {
+; CHECK-LABEL: scvtf_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf d0, w0, #32
+; CHECK-NEXT: ret
+ %cvt = sitofp i32 %int to double
+ %fix = fdiv double %cvt, 4294967296.0
+ ret double %fix
}
-define void @test_fcvtzu(float %flt, double %dbl) {
-; CHECK-LABEL: test_fcvtzu:
+define double @scvtf_f64_i64_7(i64 %long) {
+; CHECK-LABEL: scvtf_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf d0, x0, #7
+; CHECK-NEXT: ret
+ %cvt = sitofp i64 %long to double
+ %fix = fdiv double %cvt, 128.0
+ ret double %fix
+}
- %fix1 = fmul float %flt, 128.0
- %cvt1 = fptoui float %fix1 to i32
-; CHECK: fcvtzu {{w[0-9]+}}, {{s[0-9]+}}, #7
- store volatile i32 %cvt1, i32* @var32
+define double @scvtf_f64_i64_64(i64 %long) {
+; CHECK-LABEL: scvtf_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf d0, x0, #64
+; CHECK-NEXT: ret
+ %cvt = sitofp i64 %long to double
+ %fix = fdiv double %cvt, 18446744073709551616.0
+ ret double %fix
+}
+
+define half @scvtf_f16_i32_7(i32 %int) {
+; CHECK-NO16-LABEL: scvtf_f16_i32_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: scvtf s0, w0
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fdiv s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: scvtf_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: scvtf h0, w0, #7
+; CHECK-FP16-NEXT: ret
+ %cvt = sitofp i32 %int to half
+ %fix = fdiv half %cvt, 128.0
+ ret half %fix
+}
- %fix2 = fmul float %flt, 4294967296.0
- %cvt2 = fptoui float %fix2 to i32
-; CHECK: fcvtzu {{w[0-9]+}}, {{s[0-9]+}}, #32
- store volatile i32 %cvt2, i32* @var32
-
- %fix3 = fmul float %flt, 128.0
- %cvt3 = fptoui float %fix3 to i64
-; CHECK: fcvtzu {{x[0-9]+}}, {{s[0-9]+}}, #7
- store volatile i64 %cvt3, i64* @var64
-
- %fix4 = fmul float %flt, 18446744073709551616.0
- %cvt4 = fptoui float %fix4 to i64
-; CHECK: fcvtzu {{x[0-9]+}}, {{s[0-9]+}}, #64
- store volatile i64 %cvt4, i64* @var64
-
- %fix5 = fmul double %dbl, 128.0
- %cvt5 = fptoui double %fix5 to i32
-; CHECK: fcvtzu {{w[0-9]+}}, {{d[0-9]+}}, #7
- store volatile i32 %cvt5, i32* @var32
-
- %fix6 = fmul double %dbl, 4294967296.0
- %cvt6 = fptoui double %fix6 to i32
-; CHECK: fcvtzu {{w[0-9]+}}, {{d[0-9]+}}, #32
- store volatile i32 %cvt6, i32* @var32
-
- %fix7 = fmul double %dbl, 128.0
- %cvt7 = fptoui double %fix7 to i64
-; CHECK: fcvtzu {{x[0-9]+}}, {{d[0-9]+}}, #7
- store volatile i64 %cvt7, i64* @var64
-
- %fix8 = fmul double %dbl, 18446744073709551616.0
- %cvt8 = fptoui double %fix8 to i64
-; CHECK: fcvtzu {{x[0-9]+}}, {{d[0-9]+}}, #64
- store volatile i64 %cvt8, i64* @var64
-
- ret void
-}
-
- at varfloat = global float 0.0
- at vardouble = global double 0.0
-
-define void @test_scvtf(i32 %int, i64 %long) {
-; CHECK-LABEL: test_scvtf:
-
- %cvt1 = sitofp i32 %int to float
- %fix1 = fdiv float %cvt1, 128.0
-; CHECK: scvtf {{s[0-9]+}}, {{w[0-9]+}}, #7
- store volatile float %fix1, float* @varfloat
-
- %cvt2 = sitofp i32 %int to float
- %fix2 = fdiv float %cvt2, 4294967296.0
-; CHECK: scvtf {{s[0-9]+}}, {{w[0-9]+}}, #32
- store volatile float %fix2, float* @varfloat
-
- %cvt3 = sitofp i64 %long to float
- %fix3 = fdiv float %cvt3, 128.0
-; CHECK: scvtf {{s[0-9]+}}, {{x[0-9]+}}, #7
- store volatile float %fix3, float* @varfloat
-
- %cvt4 = sitofp i64 %long to float
- %fix4 = fdiv float %cvt4, 18446744073709551616.0
-; CHECK: scvtf {{s[0-9]+}}, {{x[0-9]+}}, #64
- store volatile float %fix4, float* @varfloat
-
- %cvt5 = sitofp i32 %int to double
- %fix5 = fdiv double %cvt5, 128.0
-; CHECK: scvtf {{d[0-9]+}}, {{w[0-9]+}}, #7
- store volatile double %fix5, double* @vardouble
-
- %cvt6 = sitofp i32 %int to double
- %fix6 = fdiv double %cvt6, 4294967296.0
-; CHECK: scvtf {{d[0-9]+}}, {{w[0-9]+}}, #32
- store volatile double %fix6, double* @vardouble
-
- %cvt7 = sitofp i64 %long to double
- %fix7 = fdiv double %cvt7, 128.0
-; CHECK: scvtf {{d[0-9]+}}, {{x[0-9]+}}, #7
- store volatile double %fix7, double* @vardouble
-
- %cvt8 = sitofp i64 %long to double
- %fix8 = fdiv double %cvt8, 18446744073709551616.0
-; CHECK: scvtf {{d[0-9]+}}, {{x[0-9]+}}, #64
- store volatile double %fix8, double* @vardouble
-
- ret void
-}
-
-define void @test_ucvtf(i32 %int, i64 %long) {
-; CHECK-LABEL: test_ucvtf:
-
- %cvt1 = uitofp i32 %int to float
- %fix1 = fdiv float %cvt1, 128.0
-; CHECK: ucvtf {{s[0-9]+}}, {{w[0-9]+}}, #7
- store volatile float %fix1, float* @varfloat
-
- %cvt2 = uitofp i32 %int to float
- %fix2 = fdiv float %cvt2, 4294967296.0
-; CHECK: ucvtf {{s[0-9]+}}, {{w[0-9]+}}, #32
- store volatile float %fix2, float* @varfloat
-
- %cvt3 = uitofp i64 %long to float
- %fix3 = fdiv float %cvt3, 128.0
-; CHECK: ucvtf {{s[0-9]+}}, {{x[0-9]+}}, #7
- store volatile float %fix3, float* @varfloat
-
- %cvt4 = uitofp i64 %long to float
- %fix4 = fdiv float %cvt4, 18446744073709551616.0
-; CHECK: ucvtf {{s[0-9]+}}, {{x[0-9]+}}, #64
- store volatile float %fix4, float* @varfloat
-
- %cvt5 = uitofp i32 %int to double
- %fix5 = fdiv double %cvt5, 128.0
-; CHECK: ucvtf {{d[0-9]+}}, {{w[0-9]+}}, #7
- store volatile double %fix5, double* @vardouble
-
- %cvt6 = uitofp i32 %int to double
- %fix6 = fdiv double %cvt6, 4294967296.0
-; CHECK: ucvtf {{d[0-9]+}}, {{w[0-9]+}}, #32
- store volatile double %fix6, double* @vardouble
-
- %cvt7 = uitofp i64 %long to double
- %fix7 = fdiv double %cvt7, 128.0
-; CHECK: ucvtf {{d[0-9]+}}, {{x[0-9]+}}, #7
- store volatile double %fix7, double* @vardouble
+define half @scvtf_f16_i32_15(i32 %int) {
+; CHECK-NO16-LABEL: scvtf_f16_i32_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: scvtf s0, w0
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fdiv s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: scvtf_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: scvtf h0, w0, #15
+; CHECK-FP16-NEXT: ret
+ %cvt = sitofp i32 %int to half
+ %fix = fdiv half %cvt, 32768.0
+ ret half %fix
+}
- %cvt8 = uitofp i64 %long to double
- %fix8 = fdiv double %cvt8, 18446744073709551616.0
-; CHECK: ucvtf {{d[0-9]+}}, {{x[0-9]+}}, #64
- store volatile double %fix8, double* @vardouble
+define half @scvtf_f16_i64_7(i64 %long) {
+; CHECK-NO16-LABEL: scvtf_f16_i64_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: scvtf s0, x0
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fdiv s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: scvtf_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: scvtf h0, x0, #7
+; CHECK-FP16-NEXT: ret
+ %cvt = sitofp i64 %long to half
+ %fix = fdiv half %cvt, 128.0
+ ret half %fix
+}
+
+define half @scvtf_f16_i64_15(i64 %long) {
+; CHECK-NO16-LABEL: scvtf_f16_i64_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: scvtf s0, x0
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fdiv s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: scvtf_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: scvtf h0, x0, #15
+; CHECK-FP16-NEXT: ret
+ %cvt = sitofp i64 %long to half
+ %fix = fdiv half %cvt, 32768.0
+ ret half %fix
+}
+
+; uitofp
+
+define float @ucvtf_f32_i32_7(i32 %int) {
+; CHECK-LABEL: ucvtf_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf s0, w0, #7
+; CHECK-NEXT: ret
+ %cvt = uitofp i32 %int to float
+ %fix = fdiv float %cvt, 128.0
+ ret float %fix
+}
+
+define float @ucvtf_f32_i32_32(i32 %int) {
+; CHECK-LABEL: ucvtf_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf s0, w0, #32
+; CHECK-NEXT: ret
+ %cvt = uitofp i32 %int to float
+ %fix = fdiv float %cvt, 4294967296.0
+ ret float %fix
+}
+
+define float @ucvtf_f32_i64_7(i64 %long) {
+; CHECK-LABEL: ucvtf_f32_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf s0, x0, #7
+; CHECK-NEXT: ret
+ %cvt = uitofp i64 %long to float
+ %fix = fdiv float %cvt, 128.0
+ ret float %fix
+}
+
+define float @ucvtf_f32_i64_64(i64 %long) {
+; CHECK-LABEL: ucvtf_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf s0, x0, #64
+; CHECK-NEXT: ret
+ %cvt = uitofp i64 %long to float
+ %fix = fdiv float %cvt, 18446744073709551616.0
+ ret float %fix
+}
+
+define double @ucvtf_f64_i32_7(i32 %int) {
+; CHECK-LABEL: ucvtf_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf d0, w0, #7
+; CHECK-NEXT: ret
+ %cvt = uitofp i32 %int to double
+ %fix = fdiv double %cvt, 128.0
+ ret double %fix
+}
+
+define double @ucvtf_f64_i32_32(i32 %int) {
+; CHECK-LABEL: ucvtf_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf d0, w0, #32
+; CHECK-NEXT: ret
+ %cvt = uitofp i32 %int to double
+ %fix = fdiv double %cvt, 4294967296.0
+ ret double %fix
+}
+
+define double @ucvtf_f64_i64_7(i64 %long) {
+; CHECK-LABEL: ucvtf_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf d0, x0, #7
+; CHECK-NEXT: ret
+ %cvt = uitofp i64 %long to double
+ %fix = fdiv double %cvt, 128.0
+ ret double %fix
+}
+
+define double @ucvtf_f64_i64_64(i64 %long) {
+; CHECK-LABEL: ucvtf_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf d0, x0, #64
+; CHECK-NEXT: ret
+ %cvt = uitofp i64 %long to double
+ %fix = fdiv double %cvt, 18446744073709551616.0
+ ret double %fix
+}
+
+define half @ucvtf_f16_i32_7(i32 %int) {
+; CHECK-NO16-LABEL: ucvtf_f16_i32_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: ucvtf s0, w0
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fdiv s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: ucvtf_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ucvtf h0, w0, #7
+; CHECK-FP16-NEXT: ret
+ %cvt = uitofp i32 %int to half
+ %fix = fdiv half %cvt, 128.0
+ ret half %fix
+}
+
+define half @ucvtf_f16_i32_15(i32 %int) {
+; CHECK-NO16-LABEL: ucvtf_f16_i32_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: ucvtf s0, w0
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fdiv s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: ucvtf_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ucvtf h0, w0, #15
+; CHECK-FP16-NEXT: ret
+ %cvt = uitofp i32 %int to half
+ %fix = fdiv half %cvt, 32768.0
+ ret half %fix
+}
+
+define half @ucvtf_f16_i64_7(i64 %long) {
+; CHECK-NO16-LABEL: ucvtf_f16_i64_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: ucvtf s0, x0
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fdiv s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: ucvtf_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ucvtf h0, x0, #7
+; CHECK-FP16-NEXT: ret
+ %cvt = uitofp i64 %long to half
+ %fix = fdiv half %cvt, 128.0
+ ret half %fix
+}
+
+define half @ucvtf_f16_i64_15(i64 %long) {
+; CHECK-NO16-LABEL: ucvtf_f16_i64_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: ucvtf s0, x0
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fdiv s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: ucvtf_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ucvtf h0, x0, #15
+; CHECK-FP16-NEXT: ret
+ %cvt = uitofp i64 %long to half
+ %fix = fdiv half %cvt, 32768.0
+ ret half %fix
+}
+
+
+; fptoui.sat
+
+declare i32 @llvm.fptosi.sat.i32.f32(float)
+declare i64 @llvm.fptosi.sat.i64.f32(float)
+declare i32 @llvm.fptosi.sat.i32.f64(double)
+declare i64 @llvm.fptosi.sat.i64.f64(double)
+declare i32 @llvm.fptosi.sat.i32.f16(half)
+declare i64 @llvm.fptosi.sat.i64.f16(half)
+
+define i32 @fcvtzs_sat_f32_i32_7(float %flt) {
+; CHECK-LABEL: fcvtzs_sat_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #1124073472
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fmul s0, s0, s1
+; CHECK-NEXT: fcvtzs w0, s0
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 128.0
+ %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
+ ret i32 %cvt
+}
+
+define i32 @fcvtzs_sat_f32_i32_32(float %flt) {
+; CHECK-LABEL: fcvtzs_sat_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #1333788672
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fmul s0, s0, s1
+; CHECK-NEXT: fcvtzs w0, s0
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 4294967296.0
+ %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
+ ret i32 %cvt
+}
+
+define i64 @fcvtzs_sat_f32_i64_64(float %flt) {
+; CHECK-LABEL: fcvtzs_sat_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #1602224128
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fmul s0, s0, s1
+; CHECK-NEXT: fcvtzs x0, s0
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 18446744073709551616.0
+ %cvt = call i64 @llvm.fptosi.sat.i64.f32(float %fix)
+ ret i64 %cvt
+}
+
+define i32 @fcvtzs_sat_f64_i32_7(double %dbl) {
+; CHECK-LABEL: fcvtzs_sat_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4638707616191610880
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fmul d0, d0, d1
+; CHECK-NEXT: fcvtzs w0, d0
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 128.0
+ %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
+ ret i32 %cvt
+}
+
+define i32 @fcvtzs_sat_f64_i32_32(double %dbl) {
+; CHECK-LABEL: fcvtzs_sat_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4751297606875873280
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fmul d0, d0, d1
+; CHECK-NEXT: fcvtzs w0, d0
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 4294967296.0
+ %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
+ ret i32 %cvt
+}
+
+define i64 @fcvtzs_sat_f64_i64_7(double %dbl) {
+; CHECK-LABEL: fcvtzs_sat_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4638707616191610880
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fmul d0, d0, d1
+; CHECK-NEXT: fcvtzs x0, d0
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 128.0
+ %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
+ ret i64 %cvt
+}
+
+define i64 @fcvtzs_sat_f64_i64_64(double %dbl) {
+; CHECK-LABEL: fcvtzs_sat_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4895412794951729152
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fmul d0, d0, d1
+; CHECK-NEXT: fcvtzs x0, d0
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 18446744073709551616.0
+ %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
+ ret i64 %cvt
+}
+
+define i32 @fcvtzs_sat_f16_i32_7(half %dbl) {
+; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzs w0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: adrp x8, .LCPI55_0
+; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI55_0]
+; CHECK-FP16-NEXT: fmul h0, h0, h1
+; CHECK-FP16-NEXT: fcvtzs w0, h0
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %dbl, 128.0
+ %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
+ ret i32 %cvt
+}
+
+define i32 @fcvtzs_sat_f16_i32_15(half %dbl) {
+; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzs w0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: adrp x8, .LCPI56_0
+; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI56_0]
+; CHECK-FP16-NEXT: fmul h0, h0, h1
+; CHECK-FP16-NEXT: fcvtzs w0, h0
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %dbl, 32768.0
+ %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
+ ret i32 %cvt
+}
+
+define i64 @fcvtzs_sat_f16_i64_7(half %dbl) {
+; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzs x0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: adrp x8, .LCPI57_0
+; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI57_0]
+; CHECK-FP16-NEXT: fmul h0, h0, h1
+; CHECK-FP16-NEXT: fcvtzs x0, h0
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %dbl, 128.0
+ %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
+ ret i64 %cvt
+}
+
+define i64 @fcvtzs_sat_f16_i64_15(half %dbl) {
+; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzs x0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: adrp x8, .LCPI58_0
+; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI58_0]
+; CHECK-FP16-NEXT: fmul h0, h0, h1
+; CHECK-FP16-NEXT: fcvtzs x0, h0
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %dbl, 32768.0
+ %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
+ ret i64 %cvt
+}
+
+; fptoui
+
+declare i32 @llvm.fptoui.sat.i32.f32(float)
+declare i64 @llvm.fptoui.sat.i64.f32(float)
+declare i32 @llvm.fptoui.sat.i32.f64(double)
+declare i64 @llvm.fptoui.sat.i64.f64(double)
+declare i32 @llvm.fptoui.sat.i32.f16(half)
+declare i64 @llvm.fptoui.sat.i64.f16(half)
+
+define i32 @fcvtzu_sat_f32_i32_7(float %flt) {
+; CHECK-LABEL: fcvtzu_sat_f32_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #1124073472
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fmul s0, s0, s1
+; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 128.0
+ %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
+ ret i32 %cvt
+}
+
+define i32 @fcvtzu_sat_f32_i32_32(float %flt) {
+; CHECK-LABEL: fcvtzu_sat_f32_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #1333788672
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fmul s0, s0, s1
+; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 4294967296.0
+ %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
+ ret i32 %cvt
+}
+
+define i64 @fcvtzu_sat_f32_i64_64(float %flt) {
+; CHECK-LABEL: fcvtzu_sat_f32_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #1602224128
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fmul s0, s0, s1
+; CHECK-NEXT: fcvtzu x0, s0
+; CHECK-NEXT: ret
+ %fix = fmul float %flt, 18446744073709551616.0
+ %cvt = call i64 @llvm.fptoui.sat.i64.f32(float %fix)
+ ret i64 %cvt
+}
+
+define i32 @fcvtzu_sat_f64_i32_7(double %dbl) {
+; CHECK-LABEL: fcvtzu_sat_f64_i32_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4638707616191610880
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fmul d0, d0, d1
+; CHECK-NEXT: fcvtzu w0, d0
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 128.0
+ %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
+ ret i32 %cvt
+}
+
+define i32 @fcvtzu_sat_f64_i32_32(double %dbl) {
+; CHECK-LABEL: fcvtzu_sat_f64_i32_32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4751297606875873280
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fmul d0, d0, d1
+; CHECK-NEXT: fcvtzu w0, d0
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 4294967296.0
+ %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
+ ret i32 %cvt
+}
+
+define i64 @fcvtzu_sat_f64_i64_7(double %dbl) {
+; CHECK-LABEL: fcvtzu_sat_f64_i64_7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4638707616191610880
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fmul d0, d0, d1
+; CHECK-NEXT: fcvtzu x0, d0
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 128.0
+ %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
+ ret i64 %cvt
+}
+
+define i64 @fcvtzu_sat_f64_i64_64(double %dbl) {
+; CHECK-LABEL: fcvtzu_sat_f64_i64_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4895412794951729152
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fmul d0, d0, d1
+; CHECK-NEXT: fcvtzu x0, d0
+; CHECK-NEXT: ret
+ %fix = fmul double %dbl, 18446744073709551616.0
+ %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
+ ret i64 %cvt
+}
+
+define i32 @fcvtzu_sat_f16_i32_7(half %dbl) {
+; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzu w0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: adrp x8, .LCPI66_0
+; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI66_0]
+; CHECK-FP16-NEXT: fmul h0, h0, h1
+; CHECK-FP16-NEXT: fcvtzu w0, h0
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %dbl, 128.0
+ %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
+ ret i32 %cvt
+}
+
+define i32 @fcvtzu_sat_f16_i32_15(half %dbl) {
+; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzu w0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: adrp x8, .LCPI67_0
+; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI67_0]
+; CHECK-FP16-NEXT: fmul h0, h0, h1
+; CHECK-FP16-NEXT: fcvtzu w0, h0
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %dbl, 32768.0
+ %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
+ ret i32 %cvt
+}
+
+define i64 @fcvtzu_sat_f16_i64_7(half %dbl) {
+; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_7:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1124073472
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzu x0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_7:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: adrp x8, .LCPI68_0
+; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI68_0]
+; CHECK-FP16-NEXT: fmul h0, h0, h1
+; CHECK-FP16-NEXT: fcvtzu x0, h0
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %dbl, 128.0
+ %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
+ ret i64 %cvt
+}
- ret void
+define i64 @fcvtzu_sat_f16_i64_15(half %dbl) {
+; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_15:
+; CHECK-NO16: // %bb.0:
+; CHECK-NO16-NEXT: mov w8, #1191182336
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fmov s1, w8
+; CHECK-NO16-NEXT: fmul s0, s0, s1
+; CHECK-NO16-NEXT: fcvt h0, s0
+; CHECK-NO16-NEXT: fcvt s0, h0
+; CHECK-NO16-NEXT: fcvtzu x0, s0
+; CHECK-NO16-NEXT: ret
+;
+; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_15:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: adrp x8, .LCPI69_0
+; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI69_0]
+; CHECK-FP16-NEXT: fmul h0, h0, h1
+; CHECK-FP16-NEXT: fcvtzu x0, h0
+; CHECK-FP16-NEXT: ret
+ %fix = fmul half %dbl, 32768.0
+ %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
+ ret i64 %cvt
}
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