[PATCH] D113302: [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC

Sun Nov 7 07:09:16 PST 2021

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd391e4fe841d: [X86] Update RET/LRET instruction to use the same naming convention as IRET… (authored by RKSimon).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113302/new/

https://reviews.llvm.org/D113302

Files:
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/lib/Target/X86/X86ExpandPseudo.cpp
  llvm/lib/Target/X86/X86FastISel.cpp
  llvm/lib/Target/X86/X86IndirectThunks.cpp
  llvm/lib/Target/X86/X86InstrControl.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedHaswell.td
  llvm/lib/Target/X86/X86SchedIceLake.td
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/lib/Target/X86/X86ScheduleAtom.td
  llvm/lib/Target/X86/X86ScheduleZnver1.td
  llvm/lib/Target/X86/X86ScheduleZnver2.td
  llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.mir
  llvm/test/CodeGen/MIR/X86/auto-successor.mir
  llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
  llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
  llvm/test/CodeGen/MIR/X86/block-address-operands.mir
  llvm/test/CodeGen/MIR/X86/branch-probabilities.mir
  llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
  llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
  llvm/test/CodeGen/MIR/X86/cfi-offset.mir
  llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
  llvm/test/CodeGen/MIR/X86/constant-pool.mir
  llvm/test/CodeGen/MIR/X86/constant-value-error.mir
  llvm/test/CodeGen/MIR/X86/dbg-value-list.mir
  llvm/test/CodeGen/MIR/X86/dead-register-flag.mir
  llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
  llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
  llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
  llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
  llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
  llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
  llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
  llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
  llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
  llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
  llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
  llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
  llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
  llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
  llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
  llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
  llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
  llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
  llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
  llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
  llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
  llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
  llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
  llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir
  llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
  llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
  llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
  llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
  llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
  llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
  llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
  llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
  llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
  llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir
  llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir
  llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
  llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
  llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
  llvm/test/CodeGen/MIR/X86/function-liveins.mir
  llvm/test/CodeGen/MIR/X86/global-value-operands.mir
  llvm/test/CodeGen/MIR/X86/immediate-operands.mir
  llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir
  llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
  llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir
  llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
  llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
  llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
  llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
  llvm/test/CodeGen/MIR/X86/jump-table-info.mir
  llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
  llvm/test/CodeGen/MIR/X86/killed-register-flag.mir
  llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
  llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
  llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
  llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir
  llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
  llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir
  llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir
  llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
  llvm/test/CodeGen/MIR/X86/machine-instructions.mir
  llvm/test/CodeGen/MIR/X86/machine-verifier.mir
  llvm/test/CodeGen/MIR/X86/memory-operands.mir
  llvm/test/CodeGen/MIR/X86/metadata-operands.mir
  llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir
  llvm/test/CodeGen/MIR/X86/missing-comma.mir
  llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
  llvm/test/CodeGen/MIR/X86/named-registers.mir
  llvm/test/CodeGen/MIR/X86/newline-handling.mir
  llvm/test/CodeGen/MIR/X86/null-register-operands.mir
  llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
  llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
  llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir
  llvm/test/CodeGen/MIR/X86/roundtrip.mir
  llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
  llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
  llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
  llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
  llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
  llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
  llvm/test/CodeGen/MIR/X86/stack-object-operands.mir
  llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
  llvm/test/CodeGen/MIR/X86/stack-objects.mir
  llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
  llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
  llvm/test/CodeGen/MIR/X86/subregister-operands.mir
  llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
  llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir
  llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
  llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
  llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
  llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
  llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
  llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
  llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
  llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
  llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
  llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
  llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
  llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
  llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
  llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
  llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
  llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
  llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
  llvm/test/CodeGen/MIR/X86/unknown-register.mir
  llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
  llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
  llvm/test/CodeGen/MIR/X86/unrecognized-character.mir
  llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
  llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
  llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
  llvm/test/CodeGen/MIR/X86/virtual-registers.mir
  llvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir
  llvm/test/CodeGen/X86/block-placement.mir
  llvm/test/CodeGen/X86/bug47278.mir
  llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir
  llvm/test/CodeGen/X86/dbg-value-superreg-copy.mir
  llvm/test/CodeGen/X86/evex-to-vex-compress.mir
  llvm/test/CodeGen/X86/expand-call-rvmarker.mir
  llvm/test/CodeGen/X86/expand-vr64-gr64-copy.mir
  llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir
  llvm/test/CodeGen/X86/fixup-bw-copy.mir
  llvm/test/CodeGen/X86/fixup-bw-inst.mir
  llvm/test/CodeGen/X86/implicit-null-checks.mir
  llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir
  llvm/test/CodeGen/X86/instr-symbols.mir
  llvm/test/CodeGen/X86/invalid-liveness.mir
  llvm/test/CodeGen/X86/leaFixup32.mir
  llvm/test/CodeGen/X86/leaFixup64.mir
  llvm/test/CodeGen/X86/machine-copy-dbgvalue.mir
  llvm/test/CodeGen/X86/machine-outliner-cfi-tail-some.mir
  llvm/test/CodeGen/X86/machine-outliner-cfi-tail.mir
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  llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir
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