[llvm] 14d656b - [Target] Use llvm::reverse (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 6 13:08:38 PDT 2021
Author: Kazu Hirata
Date: 2021-11-06T13:08:21-07:00
New Revision: 14d656b3d8057c4f8fa5901ad92d80b3a04fd545
URL: https://github.com/llvm/llvm-project/commit/14d656b3d8057c4f8fa5901ad92d80b3a04fd545
DIFF: https://github.com/llvm/llvm-project/commit/14d656b3d8057c4f8fa5901ad92d80b3a04fd545.diff
LOG: [Target] Use llvm::reverse (NFC)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/lib/Target/Hexagon/HexagonGenMux.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
llvm/lib/Target/X86/X86FloatingPoint.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
index e80fe2cada09..7fd51a98ad94 100644
--- a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
+++ b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
@@ -159,7 +159,7 @@ static MachineInstr *getLastNonPseudo(MachineBasicBlock &MBB,
// If there is no non-pseudo in the current block, loop back around and try
// the previous block (if there is one).
while ((FMBB = getBBFallenThrough(FMBB, TII))) {
- for (MachineInstr &I : make_range(FMBB->rbegin(), FMBB->rend()))
+ for (MachineInstr &I : llvm::reverse(*FMBB))
if (!I.isPseudo())
return &I;
}
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 16aed245b80b..1dd4f19a9fc6 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -2536,9 +2536,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
}
return true;
}
- for (auto RPII = RegPairs.rbegin(), RPIE = RegPairs.rend(); RPII != RPIE;
- ++RPII) {
- RegPairInfo RPI = *RPII;
+ for (const RegPairInfo &RPI : llvm::reverse(RegPairs)) {
unsigned Reg1 = RPI.Reg1;
unsigned Reg2 = RPI.Reg2;
unsigned StrOpc;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
index 778c7fb7ca09..b5a75032108a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
@@ -2588,11 +2588,9 @@ static bool containsNewBackedge(MRT *Tree,
}
} else {
RegionMRT *Region = Tree->getRegionMRT();
- SetVector<MRT *> *Children = Region->getChildren();
- for (auto CI = Children->rbegin(), CE = Children->rend(); CI != CE; ++CI) {
- if (containsNewBackedge(*CI, MBBs))
+ for (MRT *C : llvm::reverse(*Region->getChildren()))
+ if (containsNewBackedge(C, MBBs))
return true;
- }
}
return false;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 7f5cf157a202..cf9e22bc5ebe 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1723,8 +1723,8 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) {
bool CopyPropagation::processBlock(MachineBasicBlock &B, const RegisterSet&) {
std::vector<MachineInstr*> Instrs;
- for (auto I = B.rbegin(), E = B.rend(); I != E; ++I)
- Instrs.push_back(&*I);
+ for (MachineInstr &MI : llvm::reverse(B))
+ Instrs.push_back(&MI);
bool Changed = false;
for (auto I : Instrs) {
diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
index 8120a61a1be0..d0f36291201a 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -357,21 +357,21 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
return true;
return false;
};
- for (auto I = B.rbegin(), E = B.rend(); I != E; ++I) {
- if (I->isDebugInstr())
+ for (MachineInstr &I : llvm::reverse(B)) {
+ if (I.isDebugInstr())
continue;
// This isn't 100% accurate, but it's safe.
// It won't detect (as a kill) a case like this
// r0 = add r0, 1 <-- r0 should be "killed"
// ... = r0
- for (MachineOperand &Op : I->operands()) {
+ for (MachineOperand &Op : I.operands()) {
if (!Op.isReg() || !Op.isUse())
continue;
assert(Op.getSubReg() == 0 && "Should have physical registers only");
bool Live = IsLive(Op.getReg());
Op.setIsKill(!Live);
}
- LPR.stepBackward(*I);
+ LPR.stepBackward(I);
}
return Changed;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 6a5051f69959..76220eff4d51 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -169,13 +169,13 @@ MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB,
continue;
if (PB == BB)
continue;
- for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
- unsigned Opc = I->getOpcode();
+ for (MachineInstr &I : llvm::reverse(PB->instrs())) {
+ unsigned Opc = I.getOpcode();
if (Opc == LOOPi || Opc == LOOPr)
- return &*I;
+ return &I;
// We've reached a
diff erent loop, which means the loop01 has been
// removed.
- if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
+ if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB)
return nullptr;
}
// Check the predecessors for the LOOP instruction.
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index f644120019f8..b9311ba08065 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -322,8 +322,7 @@ static void convertUnprimedAccPHIs(const PPCInstrInfo *TII,
SmallVectorImpl<MachineInstr *> &PHIs,
Register Dst) {
DenseMap<MachineInstr *, MachineInstr *> ChangedPHIMap;
- for (auto It = PHIs.rbegin(), End = PHIs.rend(); It != End; ++It) {
- MachineInstr *PHI = *It;
+ for (MachineInstr *PHI : llvm::reverse(PHIs)) {
SmallVector<std::pair<MachineOperand, MachineOperand>, 4> PHIOps;
// We check if the current PHI node can be changed by looking at its
// operands. If all the operands are either copies from primed
diff --git a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
index 3d27b70d6ef9..254e5e92449b 100644
--- a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
@@ -211,8 +211,7 @@ bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
LiveRegs.addLiveOuts(MBB);
// Iterate backwards through the block looking for instructions to change.
- for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
- MachineInstr &MI = *MBBI;
+ for (MachineInstr &MI : llvm::reverse(MBB)) {
switch (MI.getOpcode()) {
case SystemZ::IILF:
Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
index 750734403787..c137f990ac58 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
@@ -1670,8 +1670,7 @@ void WebAssemblyCFGStackify::rewriteDepthImmediates(MachineFunction &MF) {
SmallVector<EndMarkerInfo, 8> Stack;
SmallVector<const MachineBasicBlock *, 8> EHPadStack;
for (auto &MBB : reverse(MF)) {
- for (auto I = MBB.rbegin(), E = MBB.rend(); I != E; ++I) {
- MachineInstr &MI = *I;
+ for (MachineInstr &MI : llvm::reverse(MBB)) {
switch (MI.getOpcode()) {
case WebAssembly::BLOCK:
case WebAssembly::TRY:
diff --git a/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp b/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
index 4a3206f37095..08c01ce7ba70 100644
--- a/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
+++ b/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
@@ -365,17 +365,15 @@ findPotentialBlockers(MachineInstr *LoadInst) {
PB != PE; ++PB) {
MachineBasicBlock *PMBB = *PB;
int PredCount = 0;
- for (MachineBasicBlock::reverse_iterator PBInst = PMBB->rbegin(),
- PME = PMBB->rend();
- PBInst != PME; ++PBInst) {
- if (PBInst->isMetaInstruction())
+ for (MachineInstr &PBInst : llvm::reverse(*PMBB)) {
+ if (PBInst.isMetaInstruction())
continue;
PredCount++;
if (PredCount >= LimitLeft)
break;
- if (PBInst->getDesc().isCall())
+ if (PBInst.getDesc().isCall())
break;
- PotentialBlockers.push_back(&*PBInst);
+ PotentialBlockers.push_back(&PBInst);
}
}
}
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index 67314b1dad44..8ee503e58e47 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -1733,16 +1733,14 @@ void FPS::setKillFlags(MachineBasicBlock &MBB) const {
LPR.addLiveOuts(MBB);
- for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
- I != E; ++I) {
- if (I->isDebugInstr())
+ for (MachineInstr &MI : llvm::reverse(MBB)) {
+ if (MI.isDebugInstr())
continue;
std::bitset<8> Defs;
SmallVector<MachineOperand *, 2> Uses;
- MachineInstr &MI = *I;
- for (auto &MO : I->operands()) {
+ for (auto &MO : MI.operands()) {
if (!MO.isReg())
continue;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index d352c6e4c823..33d45310af7d 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3257,13 +3257,13 @@ bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
MachineInstr *ConditionDef = nullptr;
bool SingleUseCondition = true;
- for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
- if (I->modifiesRegister(X86::EFLAGS, TRI)) {
- ConditionDef = &*I;
+ for (MachineInstr &MI : llvm::drop_begin(llvm::reverse(MBB))) {
+ if (MI.modifiesRegister(X86::EFLAGS, TRI)) {
+ ConditionDef = &MI;
break;
}
- if (I->readsRegister(X86::EFLAGS, TRI))
+ if (MI.readsRegister(X86::EFLAGS, TRI))
SingleUseCondition = false;
}
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