[llvm] 39c4c7d - [DAGCombiner] remove vselect fold that was accidentally added

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-11-06T09:34:30-04:00
New Revision: 39c4c7d3912a6759e537e03ed334451e9f96e9ad

URL: https://github.com/llvm/llvm-project/commit/39c4c7d3912a6759e537e03ed334451e9f96e9ad
DIFF: https://github.com/llvm/llvm-project/commit/39c4c7d3912a6759e537e03ed334451e9f96e9ad.diff

LOG: [DAGCombiner] remove vselect fold that was accidentally added

This diff snuck into the unrelated:
025a2f73a319

It's a suggested follow-up for D113212, but I need to add test
coverage first.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 7888712d5107e..07a2ac8db5112 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9575,23 +9575,6 @@ static SDValue foldVSelectToSignBitSplatMask(SDNode *N, SelectionDAG &DAG) {
     return DAG.getNode(ISD::OR, DL, VT, Sra, N2);
   }
 
-  // If the comparison is testing for a positive value, we have to invert
-  // the sign bit mask, so only do that transform if the target has a bitwise
-  // 'and not' instruction (the invert is free).
-  // (Cond0 s> -1) ? N1 : 0 --> ~(Cond0 s>> BW-1) & N1
-  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-  if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(Cond1) &&
-      isNullOrNullSplat(N2) && TLI.hasAndNot(N2)) {
-    SDLoc DL(N);
-    SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT);
-    SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt);
-    SDValue Not = DAG.getNOT(DL, Sra, VT);
-    return DAG.getNode(ISD::AND, DL, VT, Not, N1);
-  }
-  // (X >  0) ? X : 0 <-- This is canonical signed max.
-//    if (!(isAllOnesConstant(N1) || (isNullConstant(N1) && N0 == N2)))
-//      return SDValue();
-
   return SDValue();
 }