[PATCH] D113336: [Clang][RISCV] Let clang_cc1 be able to imply feautes

Yueh-Ting Chen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Nov 6 02:05:57 PDT 2021


eopXD created this revision.
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Under ASTContext, clang only copies the features from the options with
Target->initFeatureMap, and no implications is done there. Add implication
using RISCVISAInfo.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113336

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -796,3 +796,17 @@
 
   return Arch.str();
 }
+
+std::vector<std::string> RISCVISAInfo::toFeatureVector() const {
+  std::vector<std::string> FeatureVector;
+  for (auto Ext : Exts) {
+    std::string ExtName = Ext.first;
+    if (ExtName == "i") // i is not recognized in clang -cc1
+      continue;
+    std::string Feature = isExperimentalExtension(ExtName)
+                              ? "+experimental-" + ExtName
+                              : "+" + ExtName;
+    FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===================================================================
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -65,6 +65,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector<std::string> toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -212,7 +212,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
     Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+    std::string Buffer;
+    llvm::raw_string_ostream OutputErrMsg(Buffer);
+    handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+      OutputErrMsg << ErrMsg.getMessage();
+    });
+    Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+    return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+                                    (*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


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