[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

The title of this patch isn't descriptive of the changes in this patch. Based on the title I would only expect changes to RISCVEmitter.cpp. Can you clarify the title?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112613/new/

https://reviews.llvm.org/D112613