[PATCH] D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 5 11:13:14 PDT 2021


rampitec added a comment.

In D109301#3110900 <https://reviews.llvm.org/D109301#3110900>, @cdevadas wrote:

> In D109301#3109814 <https://reviews.llvm.org/D109301#3109814>, @rampitec wrote:
>
>> In D109301#3109806 <https://reviews.llvm.org/D109301#3109806>, @cdevadas wrote:
>>
>>> In D109301#3109750 <https://reviews.llvm.org/D109301#3109750>, @rampitec wrote:
>>>
>>>> I still do not think we can do it without solving partial spill/copy issue. At least not for wide tuples.
>>>
>>> Even today we don't generate partial spills.
>>> I am not sure how this patch is going to add any incremental impact on existing partial spill behavior.
>>
>> What do you mean? The code you are removing does it and spill-to-agpr-partial.mir in particular tests it.
>
> I see your point. The code I removed from SIFrameLowering is supposed to insert a partial tuple copy to agprs that won't happen now.
> Is it ok if we retain this code until the sub-range tuple copy/spill issue is fixed?
> In that way, we can effectively convert vector spills into a copy-to-superclass during regalloc in all possible cases. The remaining spill pseudos of tuples will get another chance for a partial copy at frame lowering.

Can you experiment with this? I am not sure it will really work and will not get first expensive wide copy and then spilling of that copied value. This at least needs a test to demonstrate how it will work.


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