[llvm] 2c4ba3e - [Target] Use make_early_inc_range (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 5 09:14:42 PDT 2021
Author: Kazu Hirata
Date: 2021-11-05T09:14:32-07:00
New Revision: 2c4ba3e9d36e9d66ece0cb48156415b65888cf95
URL: https://github.com/llvm/llvm-project/commit/2c4ba3e9d36e9d66ece0cb48156415b65888cf95
DIFF: https://github.com/llvm/llvm-project/commit/2c4ba3e9d36e9d66ece0cb48156415b65888cf95.diff
LOG: [Target] Use make_early_inc_range (NFC)
Added:
Modified:
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/lib/Target/AVR/AVRFrameLowering.cpp
llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp
llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
llvm/lib/Target/X86/X86LowerAMXType.cpp
llvm/lib/Target/X86/X86LowerTileCopy.cpp
llvm/lib/Target/X86/X86OptimizeLEAs.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 38548eaf94785..6f63f686635a5 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -1029,11 +1029,8 @@ void SIWholeQuadMode::lowerBlock(MachineBasicBlock &MBB) {
SmallVector<MachineInstr *, 4> SplitPoints;
char State = BI.InitialState;
- auto II = MBB.getFirstNonPHI(), IE = MBB.end();
- while (II != IE) {
- auto Next = std::next(II);
- MachineInstr &MI = *II;
-
+ for (MachineInstr &MI : llvm::make_early_inc_range(
+ llvm::make_range(MBB.getFirstNonPHI(), MBB.end()))) {
if (StateTransition.count(&MI))
State = StateTransition[&MI];
@@ -1051,8 +1048,6 @@ void SIWholeQuadMode::lowerBlock(MachineBasicBlock &MBB) {
}
if (SplitPoint)
SplitPoints.push_back(SplitPoint);
-
- II = Next;
}
// Perform splitting after instruction scan to simplify iteration.
diff --git a/llvm/lib/Target/AVR/AVRFrameLowering.cpp b/llvm/lib/Target/AVR/AVRFrameLowering.cpp
index a4bde546442b3..672611ea22347 100644
--- a/llvm/lib/Target/AVR/AVRFrameLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRFrameLowering.cpp
@@ -303,16 +303,16 @@ static void fixStackStores(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const TargetInstrInfo &TII, Register FP) {
// Iterate through the BB until we hit a call instruction or we reach the end.
- for (auto I = MI, E = MBB.end(); I != E && !I->isCall();) {
- MachineBasicBlock::iterator NextMI = std::next(I);
- MachineInstr &MI = *I;
- unsigned Opcode = I->getOpcode();
+ for (MachineInstr &MI :
+ llvm::make_early_inc_range(llvm::make_range(MI, MBB.end()))) {
+ if (MI.isCall())
+ break;
+
+ unsigned Opcode = MI.getOpcode();
// Only care of pseudo store instructions where SP is the base pointer.
- if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr) {
- I = NextMI;
+ if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr)
continue;
- }
assert(MI.getOperand(0).getReg() == AVR::SP &&
"Invalid register, should be SP!");
@@ -324,8 +324,6 @@ static void fixStackStores(MachineBasicBlock &MBB,
MI.setDesc(TII.get(STOpc));
MI.getOperand(0).setReg(FP);
-
- I = NextMI;
}
}
diff --git a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
index ae1f5ea21c127..7e829ea43e89f 100644
--- a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
+++ b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
@@ -97,15 +97,13 @@ void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI,
// Go through all uses of %1 as in %1 = ADD_rr %2, %3
const MachineOperand Op0 = Inst->getOperand(0);
- auto Begin = MRI->use_begin(Op0.getReg()), End = MRI->use_end();
- decltype(End) NextI;
- for (auto I = Begin; I != End; I = NextI) {
- NextI = std::next(I);
+ for (MachineOperand &MO :
+ llvm::make_early_inc_range(MRI->use_operands(Op0.getReg()))) {
// The candidate needs to have a unique definition.
- if (!MRI->getUniqueVRegDef(I->getReg()))
+ if (!MRI->getUniqueVRegDef(MO.getReg()))
continue;
- MachineInstr *DefInst = I->getParent();
+ MachineInstr *DefInst = MO.getParent();
unsigned Opcode = DefInst->getOpcode();
unsigned COREOp;
if (Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW ||
@@ -131,7 +129,7 @@ void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI,
Opcode == BPF::STD || Opcode == BPF::STB32 || Opcode == BPF::STH32 ||
Opcode == BPF::STW32) {
const MachineOperand &Opnd = DefInst->getOperand(0);
- if (Opnd.isReg() && Opnd.getReg() == I->getReg())
+ if (Opnd.isReg() && Opnd.getReg() == MO.getReg())
continue;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index 8dc26ba8206a9..7579a5e5f0b29 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -1045,13 +1045,9 @@ bool MachineConstPropagator::rewrite(MachineFunction &MF) {
// erase instructions during rewriting, so this needs to be delayed until
// now.
for (MachineBasicBlock &B : MF) {
- MachineBasicBlock::iterator I = B.begin(), E = B.end();
- while (I != E) {
- auto Next = std::next(I);
- if (I->isBranch() && !InstrExec.count(&*I))
- B.erase(I);
- I = Next;
- }
+ for (MachineInstr &MI : llvm::make_early_inc_range(B))
+ if (MI.isBranch() && !InstrExec.count(&MI))
+ B.erase(&MI);
}
return Changed;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index cb73f432375be..1d325553f45a2 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -234,16 +234,9 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
// dependence between Insn 0 and Insn 2. This can lead to incorrect
// packetization
for (MachineBasicBlock &MB : MF) {
- auto End = MB.end();
- auto MI = MB.begin();
- while (MI != End) {
- auto NextI = std::next(MI);
- if (MI->isKill()) {
- MB.erase(MI);
- End = MB.end();
- }
- MI = NextI;
- }
+ for (MachineInstr &MI : llvm::make_early_inc_range(MB))
+ if (MI.isKill())
+ MB.erase(&MI);
}
// TinyCore with Duplexes: Translate to big-instructions.
diff --git a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
index efed44d31b377..5a2c295d947e1 100644
--- a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
+++ b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
@@ -185,12 +185,9 @@ namespace {
// nothing to do.
if (MF.size() < 2)
return Changed;
-
- // We can't use a range-based for loop due to clobbering the iterator.
- for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E;) {
- MachineBasicBlock &B = *I++;
+
+ for (MachineBasicBlock &B : llvm::make_early_inc_range(MF))
Changed |= processBlock(B);
- }
return Changed;
}
diff --git a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
index 3186d197931d0..fbd487fbcfd50 100644
--- a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
@@ -208,11 +208,9 @@ namespace {
bool Changed = false;
- for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
- MachineBasicBlock &B = *I++;
+ for (MachineBasicBlock &B : llvm::make_early_inc_range(MF))
if (processBlock(B))
Changed = true;
- }
return Changed;
}
diff --git a/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp b/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp
index 3811f88e86b10..8120975c4fb25 100644
--- a/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp
@@ -131,11 +131,9 @@ namespace {
bool runOnMachineFunction(MachineFunction &MF) override {
bool Changed = false;
- for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
- MachineBasicBlock &B = *I++;
+ for (MachineBasicBlock &B : llvm::make_early_inc_range(MF))
if (processBlock(B))
Changed = true;
- }
return Changed;
}
diff --git a/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp b/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
index fd9bf96d38eba..7272e6edefc5e 100644
--- a/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
+++ b/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
@@ -148,11 +148,9 @@ namespace {
bool Changed = false;
- for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
- MachineBasicBlock &B = *I++;
+ for (MachineBasicBlock &B : llvm::make_early_inc_range(MF))
if (processBlock(B))
Changed = true;
- }
return Changed;
}
@@ -169,4 +167,3 @@ INITIALIZE_PASS(PPCVSXCopy, DEBUG_TYPE,
char PPCVSXCopy::ID = 0;
FunctionPass*
llvm::createPPCVSXCopyPass() { return new PPCVSXCopy(); }
-
diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
index de39c9c5d1f1b..0be35adc35c72 100644
--- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
+++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
@@ -361,11 +361,9 @@ namespace {
if (DisableVSXFMAMutate)
return Changed;
- for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
- MachineBasicBlock &B = *I++;
+ for (MachineBasicBlock &B : llvm::make_early_inc_range(MF))
if (processBlock(B))
Changed = true;
- }
return Changed;
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 3d60ec96ebda7..9a80394afd542 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -33838,14 +33838,11 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr &MI,
}
// Transfer any debug instructions inside the CMOV sequence to the sunk block.
- auto DbgEnd = MachineBasicBlock::iterator(LastCMOV);
- auto DbgIt = MachineBasicBlock::iterator(MI);
- while (DbgIt != DbgEnd) {
- auto Next = std::next(DbgIt);
- if (DbgIt->isDebugInstr())
- SinkMBB->push_back(DbgIt->removeFromParent());
- DbgIt = Next;
- }
+ auto DbgRange = llvm::make_range(MachineBasicBlock::iterator(MI),
+ MachineBasicBlock::iterator(LastCMOV));
+ for (MachineInstr &MI : llvm::make_early_inc_range(DbgRange))
+ if (MI.isDebugInstr())
+ SinkMBB->push_back(MI.removeFromParent());
// Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
SinkMBB->splice(SinkMBB->end(), ThisMBB,
diff --git a/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp b/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
index 248069f4deb49..08cf86b454405 100644
--- a/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
+++ b/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
@@ -498,8 +498,8 @@ X86LowerAMXIntrinsics::lowerTileDP(Instruction *TileDP) {
Value *ResAMX =
Builder.CreateBitCast(ResVec, Type::getX86_AMXTy(Builder.getContext()));
// Delete TileDP intrinsic and do some clean-up.
- for (auto UI = TileDP->use_begin(), UE = TileDP->use_end(); UI != UE;) {
- Instruction *I = cast<Instruction>((UI++)->getUser());
+ for (Use &U : llvm::make_early_inc_range(TileDP->uses())) {
+ Instruction *I = cast<Instruction>(U.getUser());
Value *Vec;
if (match(I, m_BitCast(m_Value(Vec)))) {
I->replaceAllUsesWith(ResVec);
@@ -542,9 +542,8 @@ bool X86LowerAMXIntrinsics::lowerTileLoadStore(Instruction *TileLoadStore) {
Value *ResAMX =
Builder.CreateBitCast(ResVec, Type::getX86_AMXTy(Builder.getContext()));
// Delete tileloadd6 intrinsic and do some clean-up
- for (auto UI = TileLoadStore->use_begin(), UE = TileLoadStore->use_end();
- UI != UE;) {
- Instruction *I = cast<Instruction>((UI++)->getUser());
+ for (Use &U : llvm::make_early_inc_range(TileLoadStore->uses())) {
+ Instruction *I = cast<Instruction>(U.getUser());
Value *Vec;
if (match(I, m_BitCast(m_Value(Vec)))) {
I->replaceAllUsesWith(ResVec);
diff --git a/llvm/lib/Target/X86/X86LowerAMXType.cpp b/llvm/lib/Target/X86/X86LowerAMXType.cpp
index 719cd532fc01b..8e82119f71a38 100644
--- a/llvm/lib/Target/X86/X86LowerAMXType.cpp
+++ b/llvm/lib/Target/X86/X86LowerAMXType.cpp
@@ -302,9 +302,7 @@ bool X86LowerAMXType::visit() {
Col2Row.clear();
for (BasicBlock *BB : post_order(&Func)) {
- for (BasicBlock::reverse_iterator II = BB->rbegin(), IE = BB->rend();
- II != IE;) {
- Instruction &Inst = *II++;
+ for (Instruction &Inst : llvm::make_early_inc_range(llvm::reverse(*BB))) {
auto *Bitcast = dyn_cast<BitCastInst>(&Inst);
if (!Bitcast)
continue;
diff --git a/llvm/lib/Target/X86/X86LowerTileCopy.cpp b/llvm/lib/Target/X86/X86LowerTileCopy.cpp
index 03692d1957686..d6b42145859d8 100644
--- a/llvm/lib/Target/X86/X86LowerTileCopy.cpp
+++ b/llvm/lib/Target/X86/X86LowerTileCopy.cpp
@@ -75,9 +75,7 @@ bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
for (MachineBasicBlock &MBB : MF) {
- for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end();
- MII != MIE;) {
- MachineInstr &MI = *MII++;
+ for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
if (!MI.isCopy())
continue;
MachineOperand &DstMO = MI.getOperand(0);
diff --git a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp
index 659fb632cc50d..6967a96ce83bf 100644
--- a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp
+++ b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp
@@ -653,9 +653,8 @@ bool X86OptimizeLEAPass::removeRedundantLEAs(MemOpMap &LEAs) {
// isReplaceable function.
Register FirstVReg = First.getOperand(0).getReg();
Register LastVReg = Last.getOperand(0).getReg();
- for (auto UI = MRI->use_begin(LastVReg), UE = MRI->use_end();
- UI != UE;) {
- MachineOperand &MO = *UI++;
+ for (MachineOperand &MO :
+ llvm::make_early_inc_range(MRI->use_operands(LastVReg))) {
MachineInstr &MI = *MO.getParent();
if (MI.isDebugValue()) {
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