[llvm] 085acce - [RISCV] Enable FP extensions and ABI on fixed-vectors-bitcast.ll.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 5 08:49:38 PDT 2021
Author: Craig Topper
Date: 2021-11-05T08:41:34-07:00
New Revision: 085accea3c56f6924350b82f499fe20786a12d32
URL: https://github.com/llvm/llvm-project/commit/085accea3c56f6924350b82f499fe20786a12d32
DIFF: https://github.com/llvm/llvm-project/commit/085accea3c56f6924350b82f499fe20786a12d32.diff
LOG: [RISCV] Enable FP extensions and ABI on fixed-vectors-bitcast.ll.
This improves our type coverage. We were only testing integer
insert and extract before due to the FP types not being enabled for
arguments and returns.
Differential Revision: https://reviews.llvm.org/D113217
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
index 6d24d0b440574..622df640b1a58 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
@@ -1,6 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN: -riscv-v-vector-bits-min=128 -target-abi=ilp32d < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN: -riscv-v-vector-bits-min=128 -target-abi=lp64d < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
define <32 x i1> @bitcast_v4i8_v32i1(<4 x i8> %a, <32 x i1> %b) {
; CHECK-LABEL: bitcast_v4i8_v32i1:
@@ -154,7 +158,7 @@ define half @bitcast_v2i8_f16(<2 x i8> %a) {
; CHECK-LABEL: bitcast_v2i8_f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%b = bitcast <2 x i8> %a to half
ret half %b
@@ -164,7 +168,7 @@ define half @bitcast_v1i16_f16(<1 x i16> %a) {
; CHECK-LABEL: bitcast_v1i16_f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%b = bitcast <1 x i16> %a to half
ret half %b
@@ -174,7 +178,7 @@ define float @bitcast_v4i8_f32(<4 x i8> %a) {
; CHECK-LABEL: bitcast_v4i8_f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%b = bitcast <4 x i8> %a to float
ret float %b
@@ -184,7 +188,7 @@ define float @bitcast_v2i16_f32(<2 x i16> %a) {
; CHECK-LABEL: bitcast_v2i16_f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%b = bitcast <2 x i16> %a to float
ret float %b
@@ -194,84 +198,48 @@ define float @bitcast_v1i32_f32(<1 x i32> %a) {
; CHECK-LABEL: bitcast_v1i32_f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%b = bitcast <1 x i32> %a to float
ret float %b
}
define double @bitcast_v8i8_f64(<8 x i8> %a) {
-; RV32-LABEL: bitcast_v8i8_f64:
-; RV32: # %bb.0:
-; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v9, v8, a0
-; RV32-NEXT: vmv.x.s a1, v9
-; RV32-NEXT: vmv.x.s a0, v8
-; RV32-NEXT: ret
-;
-; RV64-LABEL: bitcast_v8i8_f64:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT: vmv.x.s a0, v8
-; RV64-NEXT: ret
+; CHECK-LABEL: bitcast_v8i8_f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
%b = bitcast <8 x i8> %a to double
ret double %b
}
define double @bitcast_v4i16_f64(<4 x i16> %a) {
-; RV32-LABEL: bitcast_v4i16_f64:
-; RV32: # %bb.0:
-; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v9, v8, a0
-; RV32-NEXT: vmv.x.s a1, v9
-; RV32-NEXT: vmv.x.s a0, v8
-; RV32-NEXT: ret
-;
-; RV64-LABEL: bitcast_v4i16_f64:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT: vmv.x.s a0, v8
-; RV64-NEXT: ret
+; CHECK-LABEL: bitcast_v4i16_f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
%b = bitcast <4 x i16> %a to double
ret double %b
}
define double @bitcast_v2i32_f64(<2 x i32> %a) {
-; RV32-LABEL: bitcast_v2i32_f64:
-; RV32: # %bb.0:
-; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v9, v8, a0
-; RV32-NEXT: vmv.x.s a1, v9
-; RV32-NEXT: vmv.x.s a0, v8
-; RV32-NEXT: ret
-;
-; RV64-LABEL: bitcast_v2i32_f64:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT: vmv.x.s a0, v8
-; RV64-NEXT: ret
+; CHECK-LABEL: bitcast_v2i32_f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
%b = bitcast <2 x i32> %a to double
ret double %b
}
define double @bitcast_v1i64_f64(<1 x i64> %a) {
-; RV32-LABEL: bitcast_v1i64_f64:
-; RV32: # %bb.0:
-; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v9, v8, a0
-; RV32-NEXT: vmv.x.s a1, v9
-; RV32-NEXT: vmv.x.s a0, v8
-; RV32-NEXT: ret
-;
-; RV64-LABEL: bitcast_v1i64_f64:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT: vmv.x.s a0, v8
-; RV64-NEXT: ret
+; CHECK-LABEL: bitcast_v1i64_f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
%b = bitcast <1 x i64> %a to double
ret double %b
}
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