[PATCH] D113284: [WIP][AARCH64] Enable GEP optimizations by default

[Djordje Todorovic via Phabricator via llvm-commits]

djtodoro created this revision.
djtodoro added a project: LLVM.
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This patch enables the SeparateConstOffsetFromGEP Pass for the AARCH64 target by default. It was disabled by default with cd2334.

Targets such as PPC, AMDGPU and NPTX run Straight Line Strength Reduce, GVN and Nary Reassociate Passes along with the SeparateConstOffsetFromGEP, so that may solve the issues found back then in the AARCH64 case.

This will address the [0].

TODO: Get the data on SPEC benchmark.

[0] https://bugs.llvm.org/show_bug.cgi?id=51184

Co-authored-by: @mmatic05, @milica-lazarevic, @dmilosevic141


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113284

Files:
  llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  llvm/test/CodeGen/AArch64/O3-pipeline.ll
  llvm/test/CodeGen/AArch64/cond-br-tuning.ll


Index: llvm/test/CodeGen/AArch64/cond-br-tuning.ll
===================================================================
--- llvm/test/CodeGen/AArch64/cond-br-tuning.ll
+++ llvm/test/CodeGen/AArch64/cond-br-tuning.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -debugify-and-strip-all-safe < %s -O3 -mtriple=aarch64-eabi -verify-machineinstrs | FileCheck %s
+; RUN: llc -aarch64-enable-gep-opt=false -debugify-and-strip-all-safe < %s -O3 -mtriple=aarch64-eabi -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-linaro-linux-gnueabi"
Index: llvm/test/CodeGen/AArch64/O3-pipeline.ll
===================================================================
--- llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -77,6 +77,20 @@
 ; CHECK-NEXT:       Dominator Tree Construction
 ; CHECK-NEXT:       Interleaved Access Pass
 ; CHECK-NEXT:       Natural Loop Information
+; CHECK-NEXT:      Scalar Evolution Analysis
+; CHECK-NEXT:      Split GEPs to a variadic base and a constant offset for better CSE
+; CHECK-NEXT:      Early CSE
+; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
+; CHECK-NEXT:      Function Alias Analysis Results
+; CHECK-NEXT:      Memory SSA
+; CHECK-NEXT:      Canonicalize natural loops
+; CHECK-NEXT:      LCSSA Verifier
+; CHECK-NEXT:      Loop-Closed SSA Form Pass
+; CHECK-NEXT:      Scalar Evolution Analysis
+; CHECK-NEXT:      Lazy Branch Probability Analysis
+; CHECK-NEXT:      Lazy Block Frequency Analysis
+; CHECK-NEXT:      Loop Pass Manager
+; CHECK-NEXT:        Loop Invariant Code Motion
 ; CHECK-NEXT:       CodeGen Prepare
 ; CHECK-NEXT:       Dominator Tree Construction
 ; CHECK-NEXT:       Exception handling preparation
Index: llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
-; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
+; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -aarch64-enable-gep-opt=false -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
 
 ; This file checks that the translation from llvm IR to generic MachineInstr
 ; is correct.
Index: llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
+++ llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O0
-; RUN: llc -O3 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
+; RUN: llc -O3 -stop-after=irtranslator -aarch64-enable-gep-opt=false -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--"
 
Index: llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -123,7 +123,7 @@
 static cl::opt<bool>
     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
                  cl::desc("Enable optimizations on complex GEPs"),
-                 cl::init(false));
+                 cl::init(true));
 
 static cl::opt<bool>
     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),


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