[PATCH] D113281: [AArch64][SVE] Generate ASRD instructions for power of 2 signed divides

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15032-15034
+  case Intrinsic::aarch64_sve_asrd:
+    return DAG.getNode(AArch64ISD::SRAD_PRED, SDLoc(N), N->getValueType(0),
+                       N->getOperand(1), N->getOperand(2), N->getOperand(3));
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This doesn't look correct because `AArch64ISD::SRAD_PRED` implies inactive lanes are undef.  Perhaps you meant to use `convertMergedOpToPredOp`?


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1585
   defm LSL_ZPmI  : sve_int_bin_pred_shift_imm_left_dup< 0b0011, "lsl",  "LSL_ZPZI",  int_aarch64_sve_lsl>;
-  defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<    0b0100, "asrd", "ASRD_ZPZI", int_aarch64_sve_asrd>;
+  defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<    0b0100, "asrd", "ASRD_ZPZI", AArch64asrd_p>;
 
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I don't think you intended this change, which is likely the result of the performIntrinsicCombine issue.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113281/new/

https://reviews.llvm.org/D113281