[llvm] a7b1872 - [AArch64] Fix a bug from a pattern for uaddv(uaddlp(x)) ==> uaddlv

Jingu Kang via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 5 05:48:59 PDT 2021


Author: Jingu Kang
Date: 2021-11-05T12:48:18Z
New Revision: a7b1872593db1688c4e651f1ed8be578898d7c43

URL: https://github.com/llvm/llvm-project/commit/a7b1872593db1688c4e651f1ed8be578898d7c43
DIFF: https://github.com/llvm/llvm-project/commit/a7b1872593db1688c4e651f1ed8be578898d7c43.diff

LOG: [AArch64] Fix a bug from a pattern for uaddv(uaddlp(x)) ==> uaddlv

A pattern has selected wrong uaddlv MI. It should be as below.

uaddv(uaddlp(v8i8)) ==> uaddlv(v8i8)

Differential Revision: https://reviews.llvm.org/D113263

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrInfo.td
    llvm/test/CodeGen/AArch64/neon-uaddlv.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 6cfd2a51743a9..32ff6f4772f5e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5753,7 +5753,7 @@ def : Pat<(i32 (vector_extract (v8i16 (insert_subvector undef,
             (v4i16 (AArch64uaddv (v4i16 (AArch64uaddlp (v8i8 V64:$op))))),
             (i64 0))), (i64 0))),
           (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
-           (UADDLVv4i16v V64:$op), ssub), ssub)>;
+           (UADDLVv8i8v V64:$op), hsub), ssub)>;
 def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (AArch64uaddlp
            (v16i8 V128:$op))))), (i64 0))),
           (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),

diff  --git a/llvm/test/CodeGen/AArch64/neon-uaddlv.ll b/llvm/test/CodeGen/AArch64/neon-uaddlv.ll
index 3bc55f49f27eb..bfc288109b0c2 100644
--- a/llvm/test/CodeGen/AArch64/neon-uaddlv.ll
+++ b/llvm/test/CodeGen/AArch64/neon-uaddlv.ll
@@ -17,7 +17,7 @@ define i16 @uaddlv4h_from_v8i8(<8 x i8>* %A) nounwind {
 ; CHECK-LABEL: uaddlv4h_from_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
-; CHECK-NEXT:    uaddlv s0, v0.4h
+; CHECK-NEXT:    uaddlv h0, v0.8b
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
   %tmp1 = load <8 x i8>, <8 x i8>* %A


        


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